I think i figured out the problem, but i am not sure though. I think its due to some registers settings
I my header file for DS1337, i am using these settings
#define DS1337_SP 0x0E
#define DS1337_SP_EOSC B00000000
#define DS1337_SP_RS2 B00010000
#define DS1337_SP_RS1 B00001000
#define DS1337_SP_INTCN B00000000
#define DS1337_SP_A2IE B00000010
#define DS1337_SP_A1IE B00000001
and in DS1337 datasheet , page 10 , its define what if we want to uyse 32.768 KHz crystal. Now when i work earlier, i use to use
"0b" for binary and "0x" foir hexa decimal , now here what should i use, i am totally unaware of.
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to
logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the
RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l
activates the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied.Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status
register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is set to
logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status
register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE
bit is disabled (logic 0) when power is first applied.