Purpose and calculation of C1 and R2 between gate and source in PMOS timing circuit

Other Hardware General Electronics
1

I am working with a PMOS-based switching circuit where the PMOS turns on for 20 ms with a total period of 40 ms (i.e., a 50% duty cycle). In the schematic, there is a capacitor C1 and resistor R2 placed between the gate and source terminals of the PMOS.

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I'm trying to understand the following:

  1. What is the purpose of C1 and R2 between the gate and source of the PMOS?
  2. Will the circuit still function correctly without these components?
  3. If they are necessary, how should I calculate appropriate values for C1 and R2 based on the 20 ms ON time and 40 ms period?

Any insight or calculation approach would be greatly appreciated.

Thankyou

2

To answer questions 2 and 3 requires first answering question 1.

Where did you find this unusual circuit and what was its original purpose?

What is the result of simulating the operation in LTSpice, for various values of C1 and R2, and various choices for the PMOS device?

3

  • We need to know what is generating the input/gate pulse.

  • R2 will turn OFF the P channel MOSFET if the input ever goes High impedance.

  • What is the value of C1 ?
    It might be a speed up capacitor to turn off the MOSFET but if it is too large, might cause input driver problems.

  • R1 is normally kept when a controller is driving the gate; voltages and component values are needed.

4

Keep in mind that LTSpice voltage sources are ideal, which means that the internal resistance is zero. They are not a good model for any practical power source, driving circuit, etc.

5

It seems to me that C1 would cause a (potentially large) current from V2 to be sunk into the V1 supply (an Arduino pin?) anytime that V1 switches from HIGH to LOW...

6

In fact it's a speed down capacitor. The C1/R2 efficiency depends on the (unknown) impedance of the V1 signal source.

The ON time is affected by the V1 impedance (should be a series resistor) and the RC time constant. The period time is subject to the V1 signal.

7

  • Assume V1 goes from LOW to High Z (maybe open collector or drain ? ).
    When V1 is LOW the MOSFET is ON.
    When V1 goes HIGH Z, the capacitor transfers V2 to the gate turning OFF the MOSFET, hence speeds the turning OFF of MOSFET.

  • However, there is too much that we are not being told. :roll_eyes:

8

How are the above 2 statements linked? For example the first statement might be about what you are trying to do and the second one might be about a circuit you found on the internet that you thought might fulfil the needs of the first statement. Or not. Or something else.

I note the load on the MOSFET in the circuit is 10k, is that representative of the load you are driving? If not, then what is your intended load?

There are too many unanswered questions to be helpful, others have posed some of the questions that need answers.

What are you really trying to do?

9

Is that a desirable state? Reasonable input signals switch between HiGH and LOW. Please help me deciphering the V1 PULSE spec.

10

Probably not desirable, but certainly possible (e.g., if V1 is disconnected, powered down, or reset). It would be desirable to have a defined input on the MOSFET gate when V1 is floating.

11

The Vgs then depends on the discharge time of the C1/R2 low pass filter. That's basic electronics, isn't it?

12

  • We really need more information, maybe this is AI is testing us humans. :roll_eyes:

  • If we had this circuit, the capacitor is used to speed up the turning ON of the BJT.

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  • Similar is happening in the OP post.
    However, if C1 is large, the circuit producing V1 may short when V1 goes LOW. :grimacing:

  • Most often, V1 would be LOW/HIGH but as mentioned, the OP hasn’t given us enough information.

13

R1 and C1 serve no purpose in that circuit.
It will still function without them.

14

...then we have a very different beast.

The OP circuit connects the input directly to the gate (or base), and the RC filter goes to source (or emitter) thus increasing switching time and decreasing input impedance..

I think that figuring out the input properties will reveal more bogus with the OP circuit.

15

Then test it in the real world.
I'll have ot see if i have some P-CH MOSFETS.

Tom.... :smiley: :+1: :coffee: :australia:

16

Also relevant:

OP's identical question on edaboard.com forum

Possible (?) context:

OP's other question on edaboard.com forum

17

It seems to me that C1 increases gate capacitance, and will therefore slow down transitions. Normally that's not a good thing for a mosfet used in PWM mode - it will get hotter.