The Due's PWMC has registers for synchronizing the PWM channels...
To synchronize the PWM controller channels you just need to set the PWM Sync Channels Mode register (REG_PWM_SCM) for the given channels:
REG_PWM_SCM |= PWM_SCM_SYNC7 | PWM_SCM_SYNC6 | PWM_SCM_SYNC5 | PWM_SCM_SYNC4 | // Set the PWM channels as synchronous
PWM_SCM_SYNC3 | PWM_SCM_SYNC2 | PWM_SCM_SYNC1 | PWM_SCM_SYNC0;
Then activate channel 0, (in synchronous mode there's no need to specify channels 1-7), using the PWM enable register (PWM_ENA):
REG_PWM_ENA = PWM_ENA_CHID0; // Enable the PWM channels, (only need to set channel 0 for synchronous mode)
Finally, after loading the duty cycle update registers (REG_PWM_CDTYUPDx), trigger an update by setting Update Unlock bit (UPDULOCK) the PWM Sync Channels Update Control Register (REG_PWM_SCUC):
REG_PWM_SCUC = PWM_SCUC_UPDULOCK; // Set the update unlock bit to trigger an update at the end of the next PWM period
It's also possible to set the PWM controller to automatically update the duty cycle every timer cycle, (rather than using the trigger above), by setting the UPDM: Synchronous Channels Update Mode bitfield in the PWM Sync Channels Mode register (REG_PWM_SCM) to MODE 1.
Here's an example:
// Enable synchronous, centre-aligned, 14-bit resolution PWM at 2kHz on 8 channels
void setup() {
// PWM set-up on pins DAC1, A8, A9, A10, D9, D8, D7 and D6 for channels 0 through to 8 respectively
REG_PMC_PCER1 |= PMC_PCER1_PID36; // Enable PWM
REG_PIOB_ABSR |= PIO_ABSR_P19 | PIO_ABSR_P18 | PIO_ABSR_P17 | PIO_ABSR_P16; // Set the port B PWM pins to peripheral type B
REG_PIOC_ABSR |= PIO_ABSR_P24 | PIO_ABSR_P23 | PIO_ABSR_P22 | PIO_ABSR_P21; // Set the port C PWM pins to peripheral type B
REG_PIOB_PDR |= PIO_PDR_P19 | PIO_PDR_P18 | PIO_PDR_P17 | PIO_PDR_P16; // Set the port B PWM pins to outputs
REG_PIOC_PDR |= PIO_PDR_P24 | PIO_PDR_P23 | PIO_PDR_P22 | PIO_PDR_P21; // Set the port C PWM pins to outputs
REG_PWM_CLK = PWM_CLK_PREA(0) | PWM_CLK_DIVA(1); // Set the PWM clock A rate to 84MHz (84MHz/1)
REG_PWM_SCM |= PWM_SCM_SYNC7 | PWM_SCM_SYNC6 | PWM_SCM_SYNC5 | PWM_SCM_SYNC4 | // Set the PWM channels as synchronous
PWM_SCM_SYNC3 | PWM_SCM_SYNC2 | PWM_SCM_SYNC1 | PWM_SCM_SYNC0;
for (uint8_t i = 0; i < PWMCH_NUM_NUMBER; i++) // Loop for each PWM channel (8 in total)
{
PWM->PWM_CH_NUM[i].PWM_CMR = PWM_CMR_CALG | PWM_CMR_CPRE_CLKA; // Enable centre aligned PWM and set the clock source as CLKA
PWM->PWM_CH_NUM[i].PWM_CPRD = 21000; // Set the PWM period register 84MHz/(2*2kHz)=21000;
}
REG_PWM_ENA = PWM_ENA_CHID0; // Enable the PWM channels, (only need to set channel 0 for synchronous mode)
for (uint8_t i = 0; i < PWMCH_NUM_NUMBER; i++) // Loop for each PWM channel (8 in total)
{
PWM->PWM_CH_NUM[i].PWM_CDTYUPD = 10500; // Set the PWM duty cycle to 50% (21000/2=10500)
}
REG_PWM_SCUC = PWM_SCUC_UPDULOCK; // Set the update unlock bit to trigger an update at the end of the next PWM period
}
void loop() {}