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The A/D is disabled when ADEN is cleared. The PRADC bit shuts down more of the hardware, including the comparator. The amount of current savings is relatively small (a few percent) when in active mode. It makes more of a difference in idle mode.
In power down the clocks are all stopped. According to the datasheet the PRR register has no effect then.
At 5V I got these numbers (Atmega328p):
151uA - power down mode, ADEN = 1, PRADC = 0 // ADC enabled
151uA - power down mode, ADEN = 1, PRADC = 1 // can't shut it down unless disabled first
0.1uA - power down mode, ADEN = 0, PRADC = 0 // ADC disabled but not shut down
0.1uA - power down mode, ADEN = 0, PRADC = 1 // ADC shut down
The resolution of my DMM is 0.1uA.
I did test it without sleep mode. It was drawing a little over 15mA. This is an Atmega328p at 5V with a 16MHz crystal. There is nothing else attached to it other than decoupling capacitors and a 10K pullup resistor on reset. The datasheet indicates that it should draw less than 10mA, more than 1/3 less. I can't explain the discrepancy.
In another project I run an Atmega328p at 3V and 8MHz and the measured current (about 3mA) is in agreement with the datasheet.