So I've been trying to get my parallel load Shift Register to read in some switches. I was having a real hard time making it work. While going through it, I had trouble understanding what the point of the clock inhibitor was. I'm using TI's SN74HC165N
Playground: link removed
Datasheet: link removed
From the data sheet: "Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. "
So in my circuit, I just used a 10k pulldown resistor on the CLK_INH. I figured this should work. It needs to be low for the CLK to go low to high. And it isn't factored in while the load was low.
So what is the point of the CLK INH? Is it if you have an external clock you can't control?
edit: sorry the links are not active. I'm not allowed to yet.