Question on pwm using due

Official Hardware Mega Due
1

Hi all,

I am newbie in arduino due and recently when I am trying to get due to generate pwm, I found a behavior that I cannot explain.

I called it on pin 7, and the default frequency is 1 kHz and it uses signal from PWM clock A, no problem.

Then, I went to change register PWM clock register value and try to get it higher. According to the due cpu datasheet, when I set PREA and DIVA value so that clock A has the same frequency as MCK, I was expecting something close to 84 MHz but instead, I got a square wave of 329 kHz (still 50% duty cycle), which is clearly 84 MHz / 255.

I don't see anywhere else on the PWM section of the datasheet that one can divide the MCK frequency. So I am really confused on where is this 255 coming from. If I can make use of this extra divider, it will be really helpful.

Here is my code:

#include <SPI.h>
#define PWM_WPCR    (*(volatile unsigned long int *) 0x400940E4)  //datasheet 1053
#define PWM_CLK    (*(volatile unsigned long int *) 0x40094000) // datasheet 1020
void setup() {
    analogWrite(7, 127);

   PWM_WPCR = 0x50574D3C; // disable write protection for PWM
    PWM_CLK = 0x00000001; // clk A to MCK, disable clk B
}

I have also looked into channel mode register, but if it uses clk A or clk B, then there is only one option without any divider. Please find the link to datasheet here: http://www.atmel.com/Images/doc11057.pdf

Thanks for your time. Any help is appreciated.

F33d

2

For the PWM, the actual clock rate is the PWM frequency times the PWM count. For an 8 bit resolution, the count is 255.

Therefore the max PWM frequency with 8 bit resolution is MCK/255, as you have found.

3

Look at how analogWrite sets this all up in wiring_analog.c - in particular
the PWM period count is set from the #define PWM_MAX_DUTY_CYCLE
in the call to PWMC_SetPeriod()

The various #defines are in variant.c IIRC

4

Thanks for the help guys. I will look into that file.