Questions re: SPI with ADC122S625

Hi everyone,
I am new to SPI and I wonder if someone could be so kind and point me in the right direction re: this dual channel 12-bit ADC from National Semiconductor. I am using the hardware SPI pins, this device is the only device on the SPI bus. The MCU is a plain-jane TQFP 328P. I'd like to use the SPI.h library...

My first question is on what Mode to select with this device. The data sheet states that the channel A and channel B are clocked out on the falling edges of the SCLK input and provided serially to the MISO. No MOSI communication occurs to initiate conversions, the ADC is activated by pulling CS down. So, does is SPI Mode3 appropriate?

My second question regards the timing of the response. Looking over the timing diagrams on p. 7 of the datasheet, it appears that the conversion takes 4 SCLK cycles during which the ADC outputs just zeros. 12 bits of data for channel A follow, then 4 more zeros, and finally 12 bits of Channel B data. If CS is not pulled up at this point, the conversions continue, one every 32 SCLK cycles. Now to my question: Wouldn't it make the most sense to read 4 bytes of data immediately following pulling CS down? Having read four bytes of data, pull CS back up and then right shift the first byte by 8bits, append to that the second byte of data, ditto for bytes 3&4 to make up channel B?

Last but not least, the datasheet warns against pulling CS down while SCLK is rising. Is there a practical way to have the Arduino wait to pull CS down until SCLK is falling?

Constantin:
Last but not least, the datasheet warns against pulling CS down while SCLK is rising. Is there a practical way to have the Arduino wait to pull CS down until SCLK is falling?

The clock is only pulsed during a transfer, so you don't have to worry about that.

Constantin:
My first question is on what Mode to select with this device. The data sheet states that the channel A and channel B are clocked out on the falling edges of the SCLK input and provided serially to the MISO. No MOSI communication occurs to initiate conversions, the ADC is activated by pulling CS down. So, does is SPI Mode3 appropriate?

The diagram on page 7 of the datasheet seems to me to be a bit ambiguous in this respect.

However clocking data on normally high, but high to low seems to me to be mode 2.

See my discussion here:

Thank you Mr. Gammon! Will try tonight.

OK, tried mode 2 and got positive-only numbers, which don't make sense. Mode3 results in one set of numbers, mode0 numbers are close also. I thought Mode0 might make sense on account of the QSPI, MICROWIRE support. Anyhow, while my apparent power calculations make sense (they agree closely with a Kill-A-Watt) the relative power results do not.

I am a bit perplexed since the code in the past worked perfectly with the A/D converter found inside the Atmel. The only difference was the removal of the PhaseCal calculations since this chip allegedly samples simultaneously and advertises no phase difference between the two channels. The behavior of the chip is making me wonder if this is really the case, but I want to exhaust all other (more likely) causes first.

Two principal things to investigare that I can think of are:
There may still be a phase difference on account of the transformer and the hall-effect current sensor even though I am sampling them concurrently. It wouldn't surprise me one bit if the two didn't produce slightly different AC outputs since they're not identically wound inductors.

I also need to investigate the results produced by the ADC under steady state (i.e. DC voltage) conditions first... make sure the outputs are right... and then graduate on to AC

A third, and less likely avenue for investigation, is whether I need to make any kind of provision for the TDH, the hold time after an SCLK Falling edge, which is advertised as 6-9ns before the ADC starts to respond with its four byte response.

A logic analyzer helps with this sort of stuff. I use extensively:

Illustrates the need to put test points into designs to improve signal probe access...

Mode0 and mode3 both produce credible (but different) results. The differences are subtle so which mode is right is a good question. My quant asylum scope has a pretty steep learning curve so more on that later.