Hi all - First time poster here. I've looked around the forum and web for a detailed description of how the ATMEL MCU's define a RISING EDGE (or FALLING EDGE for that matter), but haven't been able to find what I'm looking for.
To be clear, the "functional description" of a RISING EDGE is when the voltage of an input signal transitions from LOW to HIGH - simple enough. However, if an analog signal were to SLOWLY rise from 0V to 5V over, say 30 seconds, at what point would the signal be recognized as a RISING EDGE? I realize this example is applying an analog signal to a digital input, but indulge me
If anyone could explain in detail the actual process the MCU goes through when identifying a RISING EDGE, it would help me out a lot.
Atmel's uCPU has Schmidt trigger on digital input. Consequently, transition 0->1 happened at 2.7V (5V logic), and 1->0 at 2.2V, assuming 0.5V hysteresis for regular UNO.
By amazing coincidence I was wondering the same thing just this minute: I was reading the data sheet for a Texas Instruments 7414 Schmitt Trigger inverter, where it says "Operation From Very Slow Edges". So I wondered what the significance of the slope (dV/dt) actually is.
Seems from what Magician says, the slope doesn't matter: point is that it flips or flops as it crosses VT+ or VT- regardless of how gradually that happens.
