Rising or falling edges?

Projects General Guidance
1

When measuring the frequency of a pulse train from a 555 timer, I am currently calling an Interrupt Service Routine everytime the pin sees a rising edge. Is there any advantage to changing this to a falling edge? Is it faster/easier for the logic to tell if a signal is on a falling edge (ie 5 volts down to 0) than to tell if a signal is starting to rise?
All ideas are welcome.
Thanks.

2

Nope:

  1. External Interrupts
    The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if
    enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as outputs. This
    feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled
    PCINT[23:16] pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles. The
    pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK2, PCMSK1 and PCMSK0
    Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT23...0 are
    detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes
    other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated
in the specification for the External Interrupt Control Register A – EICRA. When the INT0 or INT1 interrupts are
enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition
of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
”Clock Systems and their Distribution” on page 26. Low level interrupt on INT0 and INT1 is detected asynchronously.
This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode.
The I/O clock is halted in all sleep modes except Idle mode.

Note: Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the
Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT
and CKSEL Fuses as described in ”System Clock and Clock Options” on page 26.

3

hairbair:
When measuring the frequency of a pulse train from a 555 timer, I am currently calling an Interrupt Service Routine everytime the pin sees a rising edge. Is there any advantage to changing this to a falling edge?

No advantage one way or another.

Is it faster/easier for the logic to tell if a signal is on a falling edge (ie 5 volts down to 0) than to tell if a signal is starting to rise?

No advantage one way or another.
Lefty

All ideas are welcome.
Thanks.

4

AWOL, why'd you lock this?