Routing with big areas instead of thick traces for power components

I'm reading about power management ICs on wiki and came across this RPI 3B+ photo:

Here is the link to wiki:

So I am wondering, looking at the rpi photo, how one would tell their PCB software to route like that, with big areas instead of traces under the components. You can see the top left cap and diode (?) sit between areas. Should I create polygons and name them to the net of the component's connections for say EAGLE to make the big areas like that? Thanks.

That's one way. Then just Approve the Overlap areas when you do the DRC check.

Or draw them as wide Wires and Name them afterwards. Usually leaves a little blip of trace that you have to connect up to a real trace.

Thanks CR! I usually dislike the wide wire in EAGLE because it creates a very rounded end and no taper if I go to a thinner wire. I wonder if later EAGLE versions have more options. I'm stuck at 6.6.

7.7 does the same.

My old PCB program allows for a copper pour connected to any net, not sure if Eagle can do this.

There is an additional "rank" parameter for polygons that you can "change", which controls which polygon gets to push other polygons out of their way.

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Basically the same concept as a polygon in EAGLE. Thanks.

Thanks westfw! I didn't know that before. This is neat! It seems that higher ranked polygons are pushed around by lower ranked ones. Top left is rank 2 and bottom left is rank 1, both rectangles but rank 2 is pushed around by rank 1.