SAMD51 - Setting Up PCHCTRL for TCC??

Hey there!

I am trying to convert a whole library that runs on the SAMD21 to work on the SAMD51 range of processors. I have been going ok so far but hit a few issues when it comes to the registers that have moved around significantly.

I have this code that runs on the SAMD21 processor that I need to convert to work for the SAMD51. It is setting up the TCC timers to run off the same frequency for PWM output.

#ifdef GCLK_CLKCTRL_ID_TC1_TC2
    GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_TC1_TC2_Val));
#else
    GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_TCC0_TCC1_Val));
    while (GCLK->STATUS.bit.SYNCBUSY == 1);
    GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_TCC2_TC3_Val));
#endif
    while (GCLK->STATUS.bit.SYNCBUSY == 1);

So far I have found the following code but I don’t think it achieves what I want. I want TCC0-2 to be running from the same GCLK. I am not sure if they are connected to a specific PCHCTRL channel. I won’t be using the TC section of the SAMD51, so I am not too concerned by it.

GCLK->GENCTRL[0].reg = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL
while (GCLK->SYNCBUSY.bit.GENCTRL0);
GCLK->PCHCTRL[GCLK_CLKCTRL_IDs[tcNum]].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 0

Any assistance would be great! I am stuck on this problem for the moment.

GitHub Repository - SeeSaw SAMD51
https://github.com/wallarug/seesaw/tree/samd51support

The file in question is in this directory: bsp/bsp_timer.h

Hi wallarug,

If you require the SAMD21's and SAMD51's TCCx timer to be run at the same 48MHz frequency then it's necessary to use GCLK0 (48MHz) on the SAMD21:

GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN |        // Enable the generic clock (GCLK)
                    GCLK_CLKCTRL_GEN_GCLK0 |    // Select GCLK0
                    GCLK_CLKCTRL_ID_TCC0_TCC1;  // Route GCLK0 to TCC0 and TCC1
while (GCLK->STATUS.bit.SYNCBUSY);              // Wait for synchronization

and GCLK1 (48MHz) on the SAMD51:

GCLK->PCHCTRL[TCC0_GCLK_ID].reg = GCLK_PCHCTRL_CHEN |        // Enable the TCC0 perhipheral channel
                                  GCLK_PCHCTRL_GEN_GCLK1;    // Route generic clock 1 to TCC0