Schematic/Board layout review please.. (before I send off for pcb's)

hey gang-
been working on a project/pcb for a bit now off & on… and I think Im finally done with it…and ready to send off for PCB’s to be made.

However… since I just ‘play’ like I know what Im doing here…LOL… Id appreciate it if some other more experienced members here could take a and see if they can find any errors/problems/mistakes I made… that need to be corrected before sending out to fab house.

To give a bit of a summary on the project… there were some requirements/rules I needed to abide by…

1.) minimal Arduino circuit (minimal as I can get it and still be half way stable)
2.) no voltage regulator
3.) micro SD card
4.) limited components on top of pcb (main chip, 5 x green leds, 3x red leds w/resistors…these red led resistors had to go on top for lack of space)
5.) size is UBER tiny… (not much bigger than a micro SD socket itself
6.) had to have a custom PCB shape to retro fit into an existing prop/item.


  • there is an INNER circle (orange I think)… this is only DRAWN there to give me a visual on where I can place things…and where I cant on the top of the PCB… anything on TOP outside of the orange inner ring/circle is a PAD ONLY… for flashing the chip and FTDI communication… no components on the TOP side, outer ring/circle area it will have a ‘bezel’ over it… that circle shows the ‘window/opening’ that will display the main chip.

reference pic: (mock-up only)

  • this PCB was design to be used with the SimpleSDAudio lib posted here… that does PWM audio output on PIN9

pic of how the microSD fits in on this… (and how it east up my damn space too!) LOL

anyways…so after mocking up similar on breadboard… and testing out some things, I moved onto wrapping up the PCB…

I would appreciate a second set of eyes to look it over if anyone is bored/interested. :slight_smile:

this thing has been a challenge in CRAM-FU!.. thats for sure… LOL… but fun none-the-less… :wink:

couple things to check perhaps:

1.) the C6/C7 caps… are they even working/effective like I have them? (too far away? not correct implemented for coupling caps?)
2.) R1 resistor for set-up… all that correct? RESET/DTR…etc…?
3.) maybe board is so small/traces so small… I dont need a caps C6 & C7?.. just the MAIN 22uF cap comign off the main battery input is enough? (maybe the 22uF is to high even? not really a data sheet on a voltage regulator to read to get a ‘value’ to be used)

Here are the .sch & .brd file (Eagle)…

please let me know if there re FLAWS that need to be changed:


***one side thought I have been having is… ‘future usage’…

I know the current audio quality is not ‘great’… its staticy… and VERY loud… its more of a novelty addition, and better to have ANY sound then none) :slight_smile:

that being said… I had been reading that you can combine D9 AND D10 for dual PWM output… better quality?
And the SimpleSDAudio lib/page has some example of using D10 as an extra output for the audio…

there is of course NO ROOM on the pcb for anything else… but was thinking it might be worth looking into to add a D10 pad broken out (and of course move the SD CS pin to D4)… just in case anyone wants to hack this pcb later on for better quality?

to re-iterate I ONLY have a 100uF cap on the D9 audio output pin… nothing else, and the quality is ‘ok’ at best (still static)… maybe changing the cap… and perhaps adding a resistor would help get better output? (and time better spent then trying to add in a D10 pad?)

let me know!



anybody wanna tell me how crummy I am at this? :) and see if its 'ok' and passes the 'peer test'? :)

or maybe there is abetter forum/specific section for schematic/pcb reviews to go? in stead of here?


I cant help much with the electronic design but the PCB looks good, must have been a challenge! One thing I would do it tidy up the traces and use 45 degree angles throughout, just good practice and I'm a bit anal with it :)


yeah I'll go back and straighten things up.. (I usually do... a few times before sending out.. it happened to bite me in the 'A$$' last time!.. lol)

it was a real challenge to be honest.. (for me at least) limited room, a noob..

my concerns are about the C6/C7 caps (the coupling caps for the VCC lines).. they are not any closer to the pins than the normal 22uF cap that feeds the whole board.. wondering if even needed then? helpful still?

its VERY small board/space..

every component that I can remove, I'll do it..... I can use the space! lol...

and… bump-a-roo…

I'll try and take a gander when I get home. If I can remember...


its rather straight forward… (simple minimal Arduino circuit)… its just VERY SMALL… so following all the traces might be at worst ‘trouble some’ :slight_smile:

triple checked for ‘air-wires’ this time…(DOH!) LOL…

Here is a variant version I did last night…

there is a difference between the 2

in the second/later one…

I removed C6…

moved some components over… and made the C8 (on original schematic…C2 on new one) an 0805 footprint. …(its the cap the does DC blocking on the D9 pin for PWM audio output)…

I couldnt find a 100uF , 0603 polarized/tant cap… but I didnt find one in 0805…

definitely not cheap… but when I need: polarized and super small footprint (0603/0805)… I use these. :slight_smile:

anyways… so I removed the original C6 cap… (I think coupling cap on the AVCC pin)…to make room for this slightly larger part.

the board is SOOO small… Im not sure if any oter coupling caps are needed outside of the original 22uF cap after the battery input pads?

and since the original coupling caps on C6/C7 we not any closer to the pins… not sure if they were justified/being helpful?

maybe I have it all wrong? (good to knwo before I send out for pcb’s!)


I could have probably squeezed it on the 0603 pad… but didnt want to press my luck… (55.6 KB)

The V1_0805 file does not have the top & bottom polygons named GND. Name them, that will help with grounding and also noise a little.
Add a Gnd via over by C2 also.
The schematic, run the ERC check on it, there are several errors you need to resolve. Missing GND connection for sure, signals not going anywhere can just be eliminated at the source. No values, not a big deal, same with power connections to the SD card.
Couple right angles you could adsut, helps prevent etching undercut to have less sharp angles.

Schematic - use bigger names on the lines, have to zoom in to read anything. Same on the board if there is room - little tiny names won’t silkscreen very well either.

You have Aref grounded - not sure you want to do that. Leave it open if not using analog inputs, or connect to +5.

Edit:Net Classes, add a new Power class, 16 mil wide, use for the VCC runs.

Looks very nice all around otherwise. Nice placement of parts, routed well (with Gnd planes). Look at top & bottom layer individually, you can see the right angle traces to tweak, and also any long meandering traces that could be shortened considerably. (Reset)

Edit:Net Classes, add a new Power class, 16 mil wide, use for the VCC runs.

I ripped it up, let it autotrace, added 3-4 GND vias, here’s the result.

tasm_minimal_v1.2_0805.sch (480 KB)

tasm_minimal_v1.2_0805.brd (115 KB)

Hi Crossroads-

thanks for the look!..

I want to make sure I understand everything you suggested to ‘correct’… (so bear with me!) :slight_smile:

1.) TOP/BOTTOM Poly/GND planes… - got it!..

a.) Wonder how they got ‘un-named’? In the previous files I posted (and which these are copied from) the GND planes seemed to still be named? How did I ‘break’ the net? (speculation I know) :)… maybe when removing a trace or something?

2.) “Add a Gnd via over by C2”

a.) Can you explain bit more? Where/why? It is because of the current placement of the S+ pad? (and SCK pad on top layer) that was ‘breaking it’? I just ‘schooched’ those over a bit…

3.) Schematic - ERC check.

a.) Thanks! I usually only focus on the PCB/board layout when ti comes to errors… (I need to get into better habit of checking this (schematic) too)

  • got it on the in-pin errors… (just a habit of breaking out every pin)
  • no values - got it
  • power naming on SD component - got it.

4.) AREF -

ahh… I think That happened when I removed the capacitor in there!.. thanks!.. (I see your ‘version’ still have this as well?)

I just now am opening up your revisions/file… (I wanted to try and do it on my own while reading the advice/suggestions)

Looks alot less ‘sloppy/messy’… than mine! lol… I see I make GND ‘traces’ alot… instead of making use of/tapping the GND ‘plane’ more often… (not sure why I have that train of thought)

Im not sure what you mean by the ‘edit’ comments?

“Net Classes, add a new Power class, 16 mil wide, use for the VCC runs.”

Net Classes/New Power class??

I see the bigger/fatter trace width (16mil) used for the VCC lines/traces…

But I donttink I have ever really ‘addressed’ Net Classes before in Eagle?

I see the bigger fatter trace has the Net Class name of: 1power where all other traces have 0default in their properties… (but not sure what it does, why to use it? how to use it correctly?)

Thanks for the compliment!.. Was a bit tricky being a beginner and not having much space to begin with! lol…

(I dont know why auto trace works so good for you!.. I rarely get it to complete more than 25%…and then I have to un-do most of it…lol)

Here is the final version, should have zero errors in both schematic and boardlayout now…

AREF fixed, goes direct to VCC (taps same lines as VCC traces under chip)
all clearance errors fixed,
single pins/signals that go nowhere have been removed.
missing GND connection shave been fixed
GND plans are named (again) :wink: (55.5 KB)