SCLK for SPI output


I’m trying to configure my ADC(LM98725) registers but I’m facing a small problem, it would be great if somebody help me out. I have to configure my 16 bit ADC registers which needs 25+ clocks but right now I’m getting 16 SCLK with my 16 bit data output on MOSI pin, there is no SCLK signal without data output. How can I increase the number of SCLK for my ADC?
To write to the serial registers, the timing diagram shown in a diagram. First, SEN is toggled low. The LM98725 assumes control of the SDO pin during the first eight clocks of the command. During this period, data is clocked out of the device at the rising edge of SCLK. At the rising edge of ninth clock,the LM98725 releases control of the SDO pin. At the falling edge of the ninth clock period, the master should assume control of the SDI pin and begin issuing the new command. SDI is clocked into the LM98725 at the rising edge of SCLK. The remaining bits are composed of the “write” command bit (a zero), two device addressbits (00, 01 or 10 for the LM98725), five bit register address to be written, and the eight bit register value to be written.