jon,
I know that you're trying to build a structural model of the circuit, but I realized that the behavioral model is fairly easy to build.
I'll post the structural model in VHDL when I get the chance, but it may be a bit more work to model the circuit in C++.
/* Truth Table
PS | NS
---------
ABx | AB
---------
000 | 00
001 | 01
010 | 01
011 | 10
100 | 10
101 | 11
110 | 11
111 | 00
*/
// I/O Pins:
// clock input is interrupt0 on pin 2
#define x 3 // x input on pin 3
#define A 4 // Flip-Flop A output on pin 4
#define B 5 // Flip-Flop B output on pin 5
boolean flag(0);
byte AB (B00); // initialize output of ffa & ffb to zero
//B00 means binary 00, for example B0101 = 5
void setup(){
pinMode(3,INPUT); // x
pinMode(4,OUTPUT); // A
pinMode(5,OUTPUT); // B
attachInterrupt(0,trigger,RISING);
}
void loop(){
/* Write the outputs for ffa & ffb
using the value from AB: bit 0 holds the value for B
and bit 1 holds the value for A
*/
digitalWrite(A,bitRead(AB,1));
digitalWrite(B,bitRead(AB,0));
if (flag) {
delay(250); // delay to debounce the switch
flag--; // reset the trigger to catch the next clock
if (digitalRead(3)==1) AB = ++AB % 4;
/*
no output changes unless x=1
notice that the next state for AB is always
one more than the current state, but never more than three
*/
}
}
void trigger(){
// update the trigger
if(!flag)flag++;
}