I know because it is a phase locked loop that locks to DCF77. If I reduce the prints the lock stays exactly where it should. If I have all debug prints active the lock starts to drift out of phase. If I increase the band width while debugging the lock is able to follow faster and thus stays in phase. So I assume my code behaves as expected.
The point is I noticed it when I tried to tune the lock parameters. If the parameters would have been correct the crystal would be off by ~300ppm. I double checked with a frequency counter and the crystal is accurate to 10ppm. I checked it with the ISR active. Then I noticed that the behaviour changes if I change the print statements.
This is how I assume that the print statements cause the issue.