Lets run the circuit simulator and see what we have
You can see that after clock signal goes off, capacitor C1 begins discharging through resistor R1 and we have delayed RCK signal.
Keep in mind register datasheet to figure out logic levels for stable working.
For example for my TPIC6A595 we have:
High-level input voltage at least: 0.85VCC;
Low-level input voltage max: 0.15VCC;