ShiftOut examples contain incorrect info.

I recently started playing with a 74HC595 shift register, and the sample code for same. The samples all contain code with comments stating that the latch pin should be held low while the data is clocked into the chip, then brought high afterward, as if the chip only "listens" to the data input while the latch pin is low.

This is not a requirement of the 595. The latch input shifts the data from the shift registers to the output latches on the rising edge of that input. In fact it could do so after shifting in only one of the eight bits of data. The code simply needs to pulse the latch input after the data has been clocked in.

Generally a hardware design would be created that leaves this input high, and then clock it low and then immediately high again to latch the data.

-lilbuzz

Unless there’s a requirement in the datasheet that the latch pin must be high while clocking data in, I don’t see the difference.

Unless you’re just commenting on the comments being a little misleading…

You are quite right that there is no requirement as to whether the normal state of the latch input should normally be high or low.

And, yes, I am mainly concerned with the misleading comments.

-lilbuzz