Single I2c with multiple devices vs Multiple I2c on the microcontroller

I am confused on this topic: As it is stated here i2c suppports up to 128 different devices with the same line, IF they have different addresses.
So, you just connect 4 wires (power, gnd, sda, sdl) in parallel for all devices and you are ready to go (more here).
So, why is it considered a bonus if the microntoller has more than 1 i2c (like esp8266 vs esp32).

Is it only for the case where you want 2 devices that have the same address (like 2 same oled displays), so you can just connect the first i2c of esp32 to the first oled and the second i2c to the second oled?

Furthermore for the SPI protocol: If i use different pin for every slave (picture here), so i guess there is no conflict with addresses, why esp32 has more than one SPI compare esp8266, instead of just usual pins (that can go to chip select of the slave)?

thanks in advance

So, why is it considered a bonus if the microntoller has more than 1 i2c

There are several reasons why having multiple I2C buses might be a benefit. One is that you have more bandwidth, another is that you might have several devices with identical addresses, not to forget that it might be necessary that the processor is master for some devices and slave for another, without having at least two I2C interfaces you cannot run such a setup reliably.
Also important: You have to keep the overall bus capacitance low, otherwise you won’t get the high state fast enough by the pull-ups. Each device connected to the bus adds capacitance. So splitting all the devices to two buses increases the limit of devices you’re able to connect. You won’t reach 128 devices, even if you use two buses.

Is it only for the case where you want 2 devices that have the same address (like 2 same oled displays), so you can just connect the first i2c of esp32 to the first oled and the second i2c to the second oled?

That’s only one situation but the easiest to circumvent using an I2C multiplexer (p.e. PCA9548A).

Furthermore for the SPI protocol: If i use different pin for every slave (picture here), so i guess there is no conflict with addresses, why esp32 has more than one SPI compare esp8266, instead of just usual pins (that can go to chip select of the slave)?

As above: mostly bandwidth and capacitance although the later isn’t as important for the SPI bus as it is for I2C because SPI is not pulled passively high.

Sorry for late answer..

There are several reasons why having multiple I2C buses might be a benefit. One is that you have more bandwidth

I guess by bandwidth, we mean that multiple devices make traffic higher, so speed is lower?

the processor is master for some devices and slave for another, without having at least two I2C interfaces you cannot run such a setup reliably.

you can make a device master and slave with the same i2c..but with two different i2c you can have the same device master and slave at the same time?

As above: mostly bandwidth and capacitance although the later isn't as important for the SPI bus as it is for I2C because SPI is not pulled passively high

it looks like in i2c i have to "wait" for start bit to pass from many devices before go for another cycle(?)

I guess by bandwidth, we mean that multiple devices make traffic higher, so speed is lower?

No, a single I2C has a max. bandwidth of about 10kB/s, two of the have a theoretical bandwidth of about 20kB/s.

you can make a device master and slave with the same i2c..

Theoretically you can do that but it won't ever run reiably.

but with two different i2c you can have the same device master and slave at the same time?

Yes, although "at the same time" is a to big word in most MCU cases. But as most of it is done in hardware it's actually almost at the same time.

it looks like in i2c i have to "wait" for start bit to pass from many devices before go for another cycle(?)

I have no clue what you're writing about. What kind of start bit? UART style communication uses start bits to synchronize the recipient, but I2C doesn't have an equivalent method as it's synchronous.