Solutions to signal degradation?

I'm going to attempt to control 32 TLC5490 chips at once with my arduino mega. They can me chained together so that no matter how many chips being used they will only use 5 digital pins of the arduino. The problem occurs with the MOSI pin. The signal gets degraded as it goes into the Sin and out the Sout to the next Sin. The faster the clock speed the worse the effect. So i cant use more than 5 TLC5940 chips. I know this has been done before. Lots of people do it. Someone told me to use a SN74HC04 between every 4 chips. But im not sure how that's supposed to work. The SN74HC04 is an inverter. So HIGH goes in LOW goes out. I could understand if in the process it turned a weak degraded signal strong sharp one in the process of inverting it. But does that mean i need to use two channels of the inverter to get a strong signal that's not backwards? Will the SN74HC04 do it if i use two channels? Is there a better chip for what im doing?

You first need to explain how you’ve wired things up, in particular your clock distribution
network (you do have a clock distribution network?). Are there long cable runs? Do you
have adequate decoupling? What clock speeds?

All of the chips will be within 1 foot of each other. I plan on using a strip of the strip board to be the common signal for all of them. Anything going from the arduino to the boards and jumpers on the boards will be 22AWG solid wire. Ill draw up a wiring diagram

Attached is a wiring diagram. It’s almost to scale. That’s pretty much exactly what it will look like. I drew out the orange wires but i didnt want to draw all of them so i just labled the rest. The light blue is the important one.

clock speed is 8mhz, or 4 im not sure. but i cant use more than 4 without issues

Hi,
Check

Particularly having bypass caps on each IC, where are you getting the power supply for the ICs from?
Also some connection suggestions in the attachment.

Tom… :slight_smile:

Demystifying-the-TLC5940.pdf (628 KB)

The bypass/decoupling caps are the most important part. With your testing I would suggest writing a sketch that just lights a single LED and runs down the entire line of 32 TLCs. If that works, but sketches where larger groups of LEDs don't work, then you need more/larger decoupling caps.

If you're worried about signal degradation then the solution would be a (non-inverting) Schmitt trigger buffer.

Chagrin: If you're worried about signal degradation then the solution would be a (non-inverting) Schmitt trigger buffer.

Exactly! That's what I'm looking for. I guess I got the wrong one and it was inverting. I assume I could still use it but I would have to use twice the channels to uninvert it. The buffering caps are there, I just didn't draw them. It's powered by a 40a 5v led supply. I will be putting at least 4500uF of buffering capacitors all over this thing. I've already got one controller working with 16 multiplexed leds no problem. That signal degradation was my only limit to expanding.

You will be using 74HC14 chips for the buffering - for each chip, you use two gates in series for each line buffered, and one 74HC14 chip per buffer stage between boards.

You of course do not need to buffer BLANK or VPRG as they are not time-sensitive though it may be wise to provide a buffer for a group of boards and actually buffer all lines that leave the Arduino to travel along external wiring. Since you can control the logic in your software for these lines (BLANK and VPRG), you can of course use single-stage inverting buffers. It is arguable whether you need to buffer the MOSI-MISO data. And if you want "stiffer" buffers, you can use three gates of the 74HC14 with one inverter driving two in parallel.

(There are specific-purpose non-inverting buffer chips available, but 74HC14 are liable to be much cheaper.)

Paul__B: You will be using 74HC14 chips for the buffering - for each chip, you use two gates in series for each line buffered, and one 74HC14 chip per buffer stage between boards.

You of course do not need to buffer BLANK or VPRG as they are not time-sensitive though it may be wise to provide a buffer for a group of boards and actually buffer all lines that leave the Arduino to travel along external wiring. Since you can control the logic in your software for these lines (BLANK and VPRG), you can of course use single-stage inverting buffers. It is arguable whether you need to buffer the MOSI-MISO data. And if you want "stiffer" buffers, you can use three gates of the 74HC14 with one inverter driving two in parallel.

(There are specific-purpose non-inverting buffer chips available, but 74HC14 are liable to be much cheaper.)

Thanks, using two channels was my initial thought but I was a little unsure, since one channel delays the signal by 25ns and it would have to go through 12 in series at least, I was worried about doubling that. A 600ns delay on the sin could cause problems at the end of the chain, but ill just see how it works out. I wish I had an oscilloscope

If you daisy-chain the buffers from one board to the next, the clock signal will propagate at the same rate as the data - the delay in the TLC5940 would match that in the buffers. You would not be strobing the latch for a good 1 ms anyway.

griffin175: Attached is a wiring diagram. It's almost to scale. That's pretty much exactly what it will look like. I drew out the orange wires but i didnt want to draw all of them so i just labled the rest. The light blue is the important one.

So you're overloading the output pins of the Arduino for fast signals - every input has capacitance and you're putting a lot of capacitance on the clock line, causing it to have slow edges, which ultimately leads to failure (logic edges must be fast for a clock input otherwise you are likely to see multiple triggering). You may also have signal reflections happening with long signal runs.

Every chip needs decoupling, this alone can account for malfunction.

You need the SCLK line to be properly distributed in a tree structure, so that no output is driving too many inputs (or too long a signal line), and so that the clock signals arrive simultaneously (no skew).

If all your shift registers are in a line so that a tree network is impractical you'll have to buffer every few shift-registers and in the same sequence as the data being shifted. Say every 4 chips or every PCB. The latch signal can be lower bandwidth but you might want to buffer it too so its as fast. Try to ensure that high speed logic signals never have to run any distance (10 inches is OK, 1m would be unreliable at high speed).