I need it at SPI Mode 2, which is CPOL=1, CPHA=0. As I understand it, it means SCLK is high initially, and every time it dips down, that's when the device should capture data. Just to reassure everyone that my code sets the SPI to MODE2, here's my code:
#include <SPI.h>
#define ADC_CS 4
void setup() {
// put your setup code here, to run once:
SPI.setDataMode(SPI_MODE2, ADC_CS); // page 16
SPI.setBitOrder(MSBFIRST);
SPI.setClockDivider(8.4); //ADC: 20MHz max, DAC: 50MHz write;8MHz read
SPI.begin(ADC_CS);
SPI.transfer(4, 0x10, SPI_CONTINUE);
SPI.transfer(4, 0x11);
SPI.setDataMode(SPI_MODE0, 10);
SPI.begin(10);
SPI.transfer(10,0x00);
}
void loop() {
// put your main code here, to run repeatedly:
}
But see the screenshot. 0x10, 0x11 only show up when I tell the logic analyzer to interpret it as CPOL=0, CPHA=0. It doesn't seem to matter whether I put SPI.begin() in front of the settings or after.
AS a bonus, I set setDataMode to SPI_MODE0, just in case MODE0 meant "SCLK high" to the Arduino and the behaviour, as you can see, didn't change.
EDIT: I'm running Arduino 1.5.5, but I find it hard to believe that such an obvious flaw would be fixed in 1.5.6 if it hasn't been found by now...
I'm not certain about the Due SPI. The SPI mode (in you case the clock polarity) should be changed before the slave select is activated (taken LOW), and I don't see that on your logic analyzer. Maybe it is a bug.
OK, I put your code before any SPI initialization happens.
#include <SPI.h>
#define ADC_CS 4
void setup() {
// put your setup code here, to run once:
pinMode(4, OUTPUT);
digitalWrite(4, HIGH);
pinMode(10, OUTPUT);
digitalWrite(10, HIGH);
SPI.begin(ADC_CS);
SPI.setDataMode(SPI_MODE2, ADC_CS); // page 16
SPI.transfer(4, 0x10, SPI_CONTINUE);
SPI.transfer(4, 0x11);
SPI.begin(10);
SPI.setDataMode(SPI_MODE0, 10);
SPI.transfer(10, 0x00);
}
void loop() {
// put your main code here, to run repeatedly:
}
The "device" on pin 10 is just there so that I can see if SCLK behaves differently as I change from SPI_MODE2 to SPI_MODE0. It doesn't. Here's another screenshot....
I'm not certain about the Due SPI. The SPI mode (in you case the clock polarity) should be changed before the slave select is activated (taken LOW), and I don't see that on your logic analyzer. Maybe it is a bug.
edit: I do not see the slave select going LOW. Is that channel 0?