[Solved] Battery pack management feasibility

N-mosfets N_MOS_1 and N_MOS_2 act together as SPDT switch. They allow battery cells to be connected either in series or in parallel (for charging).

P-mosfets P_MOS_3 and P_MOS_4 interrupt connections to chargers.
P_MOS_5 interrupts connection to the load.

P_MOS_3 and P_MOS_4 are there to protect chargers from high voltage when batteries are in series configuration. (Though probably can get away without the P_MOS_3).

To monitor voltages of individual cells at later stage I will add voltage dividers and 16bit ADC.

Questions.

  • Have I connected the pull-up resistors right on p-mosfets?
  • Can I replace P_MOS_3 and P_MOS_4 with schottky diodes? Or can these be n-mosfets instead, between charger connector and the ground?
  • Is there something I missed here?

ps. At current of 1A a mosfets with R(DS)on of 5mOhm will cause a voltage drop of 0.005v. So it's probably can be safely ignored..
pps. I hope to keep this schematic scalable, to be able to connect more batteries in series (within mosfet voltage limits).

Hi,
It looks okay at a glance.

To Charge, parallel.
UC1 and UC5 open, to turn Q1 and Q5 off.
UC2 V2gateONVoltage
UC3 and UC4 = GND to give two charging circuits with common gnd.

To make it a Supply to load.
UC1 = Cell1Voltage + V1gateONVoltage
UC5 = GND
UC2 open.
UC3 open
UC4 open

I'd say you could replace Q3 and Q4 with Schottky diodes.

You will have to use logic level MOSFETs as your gate voltage, if you are using the two cells to provide gate voltage, will be less than the normal 10V required by non logic level MOSFETs.

Tom... :slight_smile:

Thanks for the reassurance Tom!
Glad to hear that I have not made there any glaringly obvious mistakes in this cirquit.