there you go :
/* r16 - reserved */
/* r17 - line */
/* r18 - div/h */
/* r19 - modulo */
/* r20 - value */
/* r21 - addr add lo */
/* r22 - addr add hi */
/* r23 - all purpose */
/* r24 - output */
// Y
/* r28 - ptr addr low */
/* r29 - ptr addr high */
// Z
/* r30 - prg addr low */
/* r31 - prg addr high */
//X
// r26 - main prg addr high
// r27 - main prd addr low
__asm__ __volatile (
".macro shift_28c\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "movw r30,r26\n\t" //might cause an error
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "LD r20,Y+\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "ldi r23,8\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "mul r20,r23\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "add r0,8\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "adc r1,0\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lsl r24\n\t" "add r30,r0\n\t" "adc r31,r1\n\t"
"out (_SFR_IO_ADDR(PORTC)),r24\n\t" "lpm r24,Z\n\t"
".endm\n\t"
".macro scan_line_m7c\n\t"
"h_sync\n\t"
"sync_1\n\t"
"delay4 136\n\t" "nop\n\t"
"delay4 160\n\t"
".endm\n\t"
".macro display_line_m7c\n\t"
"h_sync\n\t"
"sync_1\n\t" //5.7us = 114c
"delay4 23\n\t" "nop\n\t" "nop\n\t"
//19c total
"md_6c\n\t"
//"ldi r30,r26\n\t"
//"ldi r31,r27\n\t" //13c
"movw r30,r26\n\t" //might cause an error
"LD r20,Y+\n\t"
"ldi r23,8\n\t"
"mul r20,r23\n\t"
"add r0,8\n\t"
"adc r1,0\n\t"
"add r30,r0\n\t"
"adc r31,r1\n\t"
"lpm r24,Z\n\t" //13c
//
////////////////////////////////////////// 37 shifts 1036c
/*"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" "shift_28c\n\t"
"shift_28c\n\t" */
////////////////////////////////////////
"data_0\n\t" "nop\n\t" "nop\n\t"
"delay4 6\n\t" "nop\n\t" "nop\n\t"
".endm\n\t"
".macro delay4 arg\n\t"
/*"ldi r25,arg\n\t"
"ldi r16,0\n\t"
"0:\n\t"
"inc r16\n\t"
"cpi r16,r25\n\t"
"brne 0b\n\t"
"nop\n\t"*/
".endm\n\t"
".macro md_6c\n\t"
"ldi r18,r17\n\t"
"lsr r18\n\t" "lsr r18\n\t" "lsr r18\n\t"
"ldi r19,r17\n\t"
"sub r19,r18\n\t"
".endm\n\t"
".macro sync_0\n\t"
//"cbi %[portb],0\n\t"
".endm\n\t"
".macro sync_1\n\t"
//"sbi %[portb],0\n\t"
".endm\n\t"
".macro data_0\n\t"
//"cbi %[portc],0\n\t"
".endm\n\t"
".macro data_1\n\t"
//"sbi %[portc],0\n\t"
".endm\n\t"
".macro h_sync\n\t"
"sync_0\n\t"
"delay4 23\n\t" "nop\n\t"
".endm\n\t"
".macro half_short\n\t"
"sync_0\n\t"
"delay4 11\n\t" "nop\n\t" "nop\n\t"
"sync_1\n\t"
"delay4 148\n\t"
".endm\n\t"
".macro half_broad\n\t"
"sync_0\n\t"
"delay4 136\n\t" "nop\n\t"
"sync_1\n\t"
"delay4 23\n\t" "nop\n\t"
".endm\n\t"
".macro short_line\n\t" "half_short\n\t"
"half_short\n\t" ".endm\n\t"
".macro broad_line\n\t" "half_broad\n\t"
"half_broad\n\t" ".endm\n\t"
);
//37*30 characters
volatile unsigned char ptr_arr[37*30];
volatile unsigned char font [10];
void setup() {
}
void loop() {
__asm__ __volatile__ (
"main:\n\t"
"broad_line\n\t"
"broad_line\n\t"
"half_broad\n\t"
"half_short\n\t"
"short_line\n\t"
"short_line\n\t"
"ldi r17,0\n\t"
"loop0:\n\t"
"scan_line_m7c\n\t"
"inc r17\n\t"
"cpi r17,32\n\t"
"breq close0\n\t"
"jmp loop0\n\t"
"close0:\n\t"
"ldi r17,0\n\t" //240 lines
"loopa:\n\t"
"display_line_m7c\n\t" //+6c
"inc r17\n\t"
"cpi r17,240\n\t"
"breq close\n\t"
"jmp loopa\n\t"
"close:\n\t"
"ldi r17,0\n\t"
"loop1:scan_line_m7c\n\t"
"inc r17\n\t"
"cpi r17,32\n\t"
"breq close1\n\t"
"jmp loop1\n\t"
"close1:\n\t"
"short_line\n\t"
"short_line\n\t"
"short_line\n\t"
"jmp main\n\t"
:
:"x" (font),"z" (font),"y" (ptr_arr),[portb] "i" (_SFR_IO_ADDR(PORTB)),[portc] "i" (_SFR_IO_ADDR(PORTC))
:"r17"
);
}