Hello,
I found the answer by myself now:
In the mega2560 datasheet it says about the UCSRnB register bit TXENx:
The diabling of the transmitter will not become effective until ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted.
Wow - that's great! So, as the "bitClear(UCSR1B, TXEN1)" will be executed quite some time before the last byte is sent out, this uC internal pending command will already be there, waiting to be executed. Still, at 1Mbit/sec each byte takes only 10 us, so any interrupting ISR must still be quite short (but this is always a requirement for ISRs.), in order to not delay the "bitClear(UCSR1B, TXEN1)" too much.
Thomas