[SOLVED] SPI bus shifting stability .

so i am working with SPI , setting the register "SPDR" and the waiting for the flags to be set indincating that the transmission is completed is simple . but i want to mark an exact time for shifting for my CPU speed .

instead of waiting for the ending of transmission by waiting for a bit to be set in a status register . i want to output the byte then wait for an exact number of clocks then get the input .

i did manage to get this to work , but can the shifting time change under any circumstances ?? since if i use clock delays instead of waiting for flag clearance i would set a fixed waiting time for the SPI communication .

Fastest way I know:

#include <SPI.h>
#define nop asm volatile ("nop")

in setup() :

 SPI.begin();
 SPI.setClockDivider(SPI_CLOCK_DIV2 ); // 8 MHz rate

Then to send 5 bytes out, from an array for example:

SPDR = dataArray[0]; nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
SPDR = dataArray[1]; nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
SPDR = dataArray[2]; nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
SPDR = dataArray[3]; nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
SPDR = dataArray[4]; nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;

No messing with delays, just sit tight while the 8 bits are shifted out. Don’t use a for loop, that only slows things down.

Add a few asm "nop" lines can accomplish this - but expect the timing to change in the future if you recompile with a different version of the compiler. Experiment to find the lowest number of nops that works.

It is not possible to eliminate the gap between bytes entirely, the SPI logic uses a few cycles to set up each transmission.

thank you guys .

If you turn off interrupts while you blast out bytes, there are no micros() disruptions of the data either. It's noticeable when sending out large amounts.