Thanks for all the feedback!
So as you guys are saying its looking like all I need is about 3 buffer chips on the CLK pin for this to work. Would this simple one work? Simply tying all the OE to VCC permanently should achieve a good buffer and then branch each of the 4 outputs to a group of SR's right? http://www.onsemi.com/pub/Collateral/MC74HC125A-D.PDF)
Also thanks dougp for reminding me about the decoupling cap. Won't forget to add it in!
Grumpy_Mike I realize that it never stopped the shift register from working, my idea was to give it the "illusion" that it is separated into 3 groups my engaging and disengaging the latch of the ones I want to update even though I was technically sending data out to them all. I was wondering if doing so might cause problems that I didn't know about that would affect performance, which it appears is the signal degradation for connecting too many to the same CLK signal.