You obviously don't believe it, but
Whandall:
I also had to isolate a RC522 with a level shifter/buffer with inhibit/enable to make it work alongside a NRF24L01+.
I found that out in
Whandall:
I could resolve the bus contention with my setup.
I'm using an yf08e based 8-bit bidirectional level shifter to bring the voltages from the Nano to
a level that's inside the MFR522 specs, that has an output enable pin.
Too bad it has the wrong polarity to drive it by CS, so I just used a free pin to control it.
My code which works (much debug output and no real action)
#include <SPI.h>
#include <MFRC522.h>
#include <printf.h>
#include <RF24.h>
#define RST_PIN 7
#define SS_PIN 8
MFRC522 mfrc522(SS_PIN, RST_PIN);
RF24 radio(9, 10);
const byte addresses[] = "10000" "20000" "30000" "40000" "50000" "60000";
struct Pack {
byte number;
unsigned long tStamp;
} Data;
byte currentTarget;
void setup() {
pinMode(6, OUTPUT);
digitalWrite(6, LOW);
printf_begin();
Serial.begin(250000);
SPI.begin();
radio.begin();
radio.enableDynamicPayloads();
radio.setDataRate(RF24_2MBPS);
radio.printDetails();
digitalWrite(6, HIGH);
mfrc522.PCD_Init();
mfrc522.PCD_DumpVersionToSerial();
digitalWrite(6, LOW);
Serial.println(F("Scan PICC to see UID, SAK, type, and data blocks..."));
radio.printDetails();
}
void loop() {
digitalWrite(6, HIGH);
if (mfrc522.PICC_IsNewCardPresent()) {
if (mfrc522.PICC_ReadCardSerial()) {
mfrc522.PICC_DumpToSerial(&(mfrc522.uid));
}
}
digitalWrite(6, LOW);
static unsigned long lastSend;
unsigned long topLoop = millis();
if (topLoop - lastSend >= 2000) {
lastSend = topLoop;
Data.number++;
Data.tStamp = topLoop;
radio.openWritingPipe(addresses + 5 * currentTarget);
if (!radio.write(&Data, sizeof(Data))) {
Serial.print(F("Failed for #"));
Serial.print(currentTarget);
Serial.print(F(" ""));
for (byte idx = 0; idx < 5; idx++) {
Serial.write(addresses[5 * currentTarget + idx]);
}
Serial.write('"');
Serial.println();
}
if (++currentTarget > 5) {
currentTarget = 0;
}
}
}
STATUS = 0x0e RX_DR=0 TX_DS=0 MAX_RT=0 RX_P_NO=7 TX_FULL=0
RX_ADDR_P0-1 = 0x3030303034 0xc2c2c2c2c2
RX_ADDR_P2-5 = 0xc3 0xc4 0xc5 0xc6
TX_ADDR = 0x3030303034
RX_PW_P0-6 = 0x20 0x00 0x00 0x00 0x00 0x00
EN_AA = 0x3f
EN_RXADDR = 0x03
RF_CH = 0x4c
RF_SETUP = 0x08
CONFIG = 0x0e
DYNPD/FEATURE = 0x3f 0x04
Data Rate = 2MBPS
Model = nRF24L01+
CRC Length = 16 bits
PA Power = PA_MIN
Firmware Version: 0x11 = (unknown)
Scan PICC to see UID, SAK, type, and data blocks...
STATUS = 0x0e RX_DR=0 TX_DS=0 MAX_RT=0 RX_P_NO=7 TX_FULL=0
RX_ADDR_P0-1 = 0x3030303034 0xc2c2c2c2c2
RX_ADDR_P2-5 = 0xc3 0xc4 0xc5 0xc6
TX_ADDR = 0x3030303034
RX_PW_P0-6 = 0x20 0x00 0x00 0x00 0x00 0x00
EN_AA = 0x3f
EN_RXADDR = 0x03
RF_CH = 0x4c
RF_SETUP = 0x08
CONFIG = 0x0e
DYNPD/FEATURE = 0x3f 0x04
Data Rate = 2MBPS
Model = nRF24L01+
CRC Length = 16 bits
PA Power = PA_MIN
Failed for #0 "10000"
Failed for #1 "20000"
Failed for #2 "30000"
Failed for #3 "40000"
Failed for #4 "50000"
Card UID: 9E 07 41 C5
Card SAK: 08
PICC type: MIFARE 1KB
Sector Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AccessBits
15 63 00 00 00 00 00 00 FF 07 80 69 FF FF FF FF FF FF [ 0 0 1 ]
62 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 0 0 0 ]
61 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 0 0 0 ]
60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 0 0 0 ]
14 59 00 00 00 00 00 00 FF 07 80 69 FF FF FF FF FF FF [ 0 0 1 ]
58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 0 0 0 ]
57 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 0 0 0 ]
56 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 0 0 0 ]
** rest of dump removed, 9000 char limit **
Failed for #5 "60000"
The failed sends are caused by the missing receiver.
With an inverter CS could be used directly and that would not require the manual disabling of the buffer.
I had a quick glance at the datasheet of the MFR, it should behave differently.