while reading about spi interface in wikipedia i seen this
The master then transmits the logic 0 for the desired chip over the chip select line. A logic 0 is transmitted because the chip select line is active low, meaning its off state is a logic 1; on is asserted with a logic 0. If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles.
to select slave we have to give low signal in slave by master.it means logic 0.but here its given as logic 1,little confusing help me please