SPI MISO from SPI slave could have long discharging tail

I set up a SPI connection between two Nanos. I found from scope that if the last bit of MISO byte (from SPI slave) is high, there is a long discharging tail, which should mean when SS_bar is high, MISO has no path to ground? If I put a 10K ohm resistor from MISO to ground, I can see the discharging is much short.

Is there any setting to avoid such issue?

dtung:
there is a long discharging tail, which should mean when SS_bar is high, MISO has no path to ground?

Forgive my ignorance, but does it matter?

...R

Robin2:
but does it matter?

...R

Judging from functionality, it doesn't matter. But I don't know whether it will cause problem later or not.

I believe that it is just the SPI slave disconnecting from the SPI bus, which it needs to do if you have multiple slave devices.

markd833:
I believe that it is just the SPI slave disconnecting from the SPI bus, which it needs to do if you have multiple slave devices.

Thanks for the response.

You are saying that many SPI slave's MISOs can wiring or together to SPI master's MISO, and the SPI master just polling SPI slaves with separate SS_bar one by one? That makes sense.

So that is a feature not a bug, I will close this question.

You can have several SPI slave devices all sharing MOSI, MISO & SCLK. Each device has a separate chip select signal.