SPI Slave Interrupt Generated By What ??

After 6 years reading and getting information, Thank You all.

On Uno to Uno, Master to Slave as shown and documented on Nick Gammon web page, i was testing and curious as to what causes an interrupt "ISR(SPI_STC_Vector)" on the Slave.
I tied the SS pin on the Slave Uno to ground Vs to the SS pin on the Master.
Suprise, the demo sketch from Nick Gammon still works just like it should and the Slave goes through the Interrupt Vector.
So question is what causes the Interrupt to trigger. Is there an 8 bit counter which fires after 8 clock pulses?

This vector ISR(TIMER2_COMPA_vect) belongs to timer2, an 8 bit timer, and is not primarily related to what looks like an example of SPI communication between two UNOs which you are referring to.

The timer has a counter register which increments, usually related to the system clock. When a defined threshold has been reached, the ISR can trigger. All the parameters for this timer are specified in the ATmega328p data sheet.

Include the code which you found in your next post if you need more specific information.

Oops Sorry about that error in original posting. It should have read " i was testing and curious as to what causes an interrupt "ISR(SPI_STC_Vector)" on the Slave." Not the ISR(TIMER2_COMP_vect.

See Section 19.2 of the ATMega328P datasheet.

RandyGa:
So question is what causes the Interrupt to trigger. Is there an 8 bit counter which fires after 8 clock pulses?

I would certainly hope so! You wouldn't want a receive interrupt to occur BEFORE the data had arrived.

RandyGa:
[...] i was testing and curious as to what causes an interrupt "ISR(SPI_STC_Vector)" on the Slave.
I tied the SS pin on the Slave Uno to ground Vs to the SS pin on the Master. [...]

Let us see the source of SPI interrupt with the help of the following diagram (Fig-1):

spi328x.png
Figure-1:

When Master executes this code SPDR = 0x23 (or SPI.transfer(0x23), 8 clock pulses are automatically generated on the SCK line to shift-in the data bits into the SPDR Register (SPI Data Register) of Slave.

Assuming SPI speed is 1 Mbits/s, then the above data will take 8 us ((1/1000000)*8) time to reach to the SPDR Register of Slave. Once, the data is present/ready in the SPDR Register of the Slave, the SPIF flag/bit of the SPSR (SPI Status Register) asumes HIGH state. If interrupt logic is already enabled, then this SPIF flag will interrupt the MCU (Fig-2). As a result, the MCU will suspend the "Main Line Program (MLP)" and then will automatically jump to the following ISR routine. (There is no way we can change these words: ISR (Interrupt Service Routine), SPI (Serial Peripheral Interface), STC Serial Transfer Complete), vect (Vectoring at this particular ISR) of the ISR routine.)

ISR(SPI_STC_vect)
{
    //insert minimum codes here; data ready in SPDR; read data but do not print here
}


Figure-2: Role of SPIF flag to generate SPI interrupt.

The following pdf document and this post may worth reading on SPI Communication.

Ch-7OnlineLec.pdf (291 KB)

spi328x.png

Thank you gavalvo. i re-read that part of the ATMega328 Data sheet . From the information in the Data Sheet it looks like after shifting 8 bits out via the SPI clock, the clock stops and sets the SPIF in SPI Contol Register.

Section 19.2 of the ATMega328P datasheet.
" writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF)."

The Slave clocks data in of course using SCK and after 8 SCK clocks it it sets the SPIF which generates an interrupt.

So, in the configuration i am using, there is no connection from Master SS to Slave SS. The Slave SS (pin 10) is tied to ground (LOW) and i dump data from Master to Slave as required and a interrupt (ISR) is gererated for the Slave to store off the incoming byte in the ISR routine for further procesing later.
i just didn't know where/what was setting SPIF to flag the interrupt. Its after the slave gets 8 SCK clock pulses.

Thank you gavalo for pointing me in the right dirrection

RandyGa:
From the information in the Data Sheet it looks like after shifting 8 bits out via the SPI clock, the clock stops and sets the SPIF in SPI Contol Register.

In fact, the SPIF flag/bit is located in the SPSR Register (SPI Status Register, Fig-1) and not in the SPCR Register (SPI Control Register, Fig-2).


Figure-1: Bit layout of SPSR Register


Figure-2: Bit layout of SPCR Register

Thank you GolamMostafa. I typed it wrong on input...