# Stepping down 12V signal to 5V

I have a 12V signal that I need to analyzer with my logic analyzer. It only supports 5V input. Will it work to use a voltage divider to reduce the voltage, or is there a way to use a transistor to have the 12V switch a 5V circuit on and off. 12V signal is digital signal.

CD4050 CMOS to T TL coverter chlp

A voltage divider would work, but, I would feed the signal into a transistor circuit.
Watch out if you use the CE NPN configuration as the output will be inverted.

CD4050 is easiest solution.

cd74hc4050 would give you nice clean signal to work with

But a simple transistor circuit is all you need for 1 signal:

But a divider is much simpler than both.

Thanks for the responses guys! I have the necessary components to try a divider and transistor idea, and if that doesn't work, I will get one of the chips.

But a simple transistor circuit is all you need for 1 signal:

What kind of value resistors would I need? I need it to be non-inverting. I have both PNP and NPN Transistors

Then use Crossroad's bottom right hand image.
Start with a base resistor of 4.7K and a collector resistor of 1.5K.

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Perfect. Will try that tonight! Again, thanks for the help!

Then use Crossroad's bottom right hand image.
Start with a base resistor of 4.7K and a collector resistor of 1.5K.

PNP for non-inverting

The reason for that is that an NPN transistor would invert the signal but a PNP turns on with a LOW, pulling the emitter output to 0V so there is no inversion.

Thanks, I was kind of curious why a PNP would produce a non-inverted, I was under the assumption that PNP's turn on when LOW.

CR, did you draw that with a foil?

outsider:
CR, did you draw that with a foil?

CR, did you draw that with a foil?

No, that's just the way he draws... ;D

Both pnp's and npn's can be wired to be either inverting ior non - inverting ( an emitter follower )
I enclose the standard configurations .

Note the catch diodes for the PNP versions to avoid over reverse-biasing the transistors

Note also that the non inverting cofiguration will only pull to within 0.7v of the +ve rail (NPN) or -ve rail (PNP)

both would be fine in logic analyser use.

But the 4050 is probably a better idea anyway.

regards

Allan.

emfol.pdf (22.2 KB)