I played with T2_TWI and T4_TWI in USI_TWI_Master.h. I changed the default values of 5/4 (1MHz) to 0.625/0.5 (divided by 8 for 8MHz) and 0.3/0.42 (divided by 16.5 for 16.5MHz).
These values are used for a call to _delay_us(), so you don't have to divide them by 8 for the 8MHz version. I would try to modify them only slightly. In my understanding you would have to increase them and not decrease them as they control the SCL speed. The sum of them plus the time needed for the few statements in the transfer routine should be around 10µs, so you might want to try 5.5 and 4.5.
I tried with DrAzzy's ATTinyCore AVR-Wire-library - but gave up in an early state because of so many compiler errors.
What core do you use?