Syncronizing Timer0,Timer1, Timer2 PWM outputs

I can’t seem to synchronize the 16-bit Timer1 output with the 8-bit Timer0 and Timer2 outputs. I want to clarify that I am able to synchronize Timer0 and Timer2 with each other but Timer1 is proving very difficult to match. I feel I am missing something. Here’s my setup() code:

GTCCR = (1<<TSM)|(1<<PSRASY)|(1<<PSRSYNC); // Halt all Timers
   
   // TIMER1 settings --------------------------------------------------
   TCCR1A = 0; // Reset TIMER 1 Control Register A
   TCCR1B = 0; // Reset TIMER 1 Control Register B
  
   TCCR1A |= (1 << COM1A1) | // 
             (0 << COM1A0) | // Clear OC1A on Compare match up counting
             (1 << COM1B1) | //
             (1 << COM1B0) | // Set OC1B on Compare match up counting
             (0 << WGM10)  |
             (1 << WGM11)  ; 
   TCCR1B |= (0 << WGM12)  |
             (0 << WGM13)  | // PWM Phase Freq correct, TOP=0x01FF, switching freq 15.63kHz
             (1 << CS10)   ; // No Prescalar
   
  
  // TIMER1 default dutycycle 
     OCR1A = 0xFF-DEADTIMECNT;
     OCR1B = 0xFF+DEADTIMECNT;   
    
  // TIMER1 interrupt settings
  TIMSK1 = 0; // Reset Timer1 interrupt mask register
  TIMSK1 |= (1 << TOIE1) ;  // TIMER2 Overflow interrupt TOV1 bit set when TCN1=BOTTOM  
  
   // TIMER 0 settings-------------------------------------------
   TCCR0A = 0; // Reset TIMER 0 Control Register A
   TCCR0B = 0; // Reset TIMER 0 Control Register B
   TCCR0A |= (1 << COM0A1); // Phase correct PWM, COM0A1=1, COM0A0=0
   TCCR0A |= (1 << COM0B1); // Phase correct PWM, COM0B1=1, COM0B0=1 
   TCCR0A |= (1 << COM0B0); 
   TCCR0A |= (1 << WGM00); // Phase correct PWM, TOP=0xFF, WGM00=1, WGM01=0, WGM02=1, Mode 1
   TCCR0B |= (1 << CS00); // CLK-I/O, No prescaling
   
   OCR0A = 0x7F-DEADTIMECNT;
   OCR0B = 0x7F+DEADTIMECNT;    
  
    
  // TIMER2 settings -------------------------------------------------------
  TCCR2A = 0; // Reset TIMER 2 Control Register A
  TCCR2B = 0; // Reset TIMER 2 Control Register B
  
  TCCR2A |= (1 << COM2A1) | // 
            (0 << COM2A0) | // Clear OC2A on Compare match up counting
            (1 << COM2B1) | //
            (1 << COM2B0) | // Set OC2B on Compare match up counting
            (1 << WGM20)  |
            (0 << WGM21)  ; // PWM Phase correct, TOP=0xFF, 31.37kHz
  TCCR2B |= (0 << WGM22)  |// 
            (1 << CS20)   ; // No Prescalar
  
   // TIMER2 default dutycycle 
    OCR2A = 0x7F-DEADTIMECNT;
    OCR2B = 0x7F+DEADTIMECNT;   
     
  // TIMER2 interrupt settings
   TIMSK2 = 0; // Reset Timer2 Interrupt mask register
   TIMSK2 |= (1 << TOIE2) ;  // TIMER2 Overflow interrupt TOV2 bit set when TCN2=BOTTOM  
  
  // TIMER2 asynchronus status register
  ASSR = 0; // Reset Async status register, TIMER2 clk = CPU clk
  
      // set all timers to the same value
  TCNT0 = 0x00; // set timer0 to 0
  TCNT1 = 0x0000; // set timer1 to 0
  TCNT2 = 0x00; // set timer2 to 0
  
  GTCCR = 0;  // release all timers

I figured out that this is happening because the number of clock cycles in 16 bit Timer1 is NOT an exact multiple of clock cycles in Timer0 or Timer2.

Perhaps if you explain why you want to synchronize the timers we could give more useful advice? What is the ultimate purpose of this?

I guess my sense is that their independence is their strength.

...R

Thanks for replying, Robin2.
I felt that if everything is synchronized to the same timebase, the timer interrupts would be more predictable and not overlap each other. But I changed my code to use a single interrupt, so this is no longer an issue. I think I will close the thread now, as soon as I figure out how to do that.

parsec326:
, as soon as I figure out how to do that.

Go back to your first post in the Thread, click Modify and add the word CLOSED or SOLVED to the title. But please DO NOT delete the title because doing so means others have no idea what the Thread was about.

Of course that won't stop other people adding to the Thread if they feel like it.

And, by the way, I suspect that synchronizing the clocks would be more likely to increase the risk of simultaneous interrupts rather than to reduce it.

...R