The Atmel datasheet uses the phrase "overflow" or "match" when describing the timer/counter interrupts. To me, these imply counting up, not down.
Can I assume that in "normal" mode (not any of the PWM modes), if the count direction bit is set to "down," an overflow interrupt will occur when the counter reaches zero? Or maybe when it counts down one more clock to 0xFF? It's not super critical to my application one way or the other, I just want an interrupt at "BOTTOM" plus or minus one prescaler cycle.
The interrupt service routine will then write a new value to the TCNT2 (Clock/timer register) to start a new countdown to the next interrupt. I'd use CTC mode, except the count for the next interrupt will differ each cycle.