transfer hundreds of bits with SPI without delay in between

Hi,

I need to send hundreds of bits to a custom chip and from what i understand, there is a delay between each SPI transfer. Dont know too much about SPI, but if the clock keeps going during the delay between the transfers, that is bad as it will shift wrong data down in the chip.

Here is a bit of the transfer code, I do calculations outside of the transfer block hoping if transfers are right next to each other there is no delay but I found out there is delay by default.. Is there any way to get rid of the delay? does clock stop right after the last bit of the transfer by any chance? if not what would be the best way to approach this? bit banging using software? would prefer to use SPI for the speed..

SPI.transfer16(0x0000); SPI.transfer16(rowContainer1); SPI.transfer(0x00); SPI.transfer16(colContainer1); SPI.transfer16(0x0180);

thank you

I've sent out bursts of 45 bytes like this:

disable interrupts
digitalWrite (ssPin, LOW);
spdr = array[0]; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
spdr = array[1]; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
spdr = array[2]; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
:
:
spdr = array[43]; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
spdr = array[44]; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
digitalWrite (ssPin, HIGH);
turn interrupts back on

The nop's give the SPI shift register time to complete the 8-bit transfer and then start the next one without the SPI library waiting for an interrupt to tell the code to start the next byte. Turning off interrupts keeps the 1uS (4uS?) interrupt from disrupting the burst. After SPI.begin() in setup, call the SPI clock divisor command to set it for 2 tor 8 MHz SPI clock. Not using a loop for the sprd calls means you don't add 8-12 uS between transfers while a for loop is incremented and checked for the end condition. Each byte then takes 17 clocks to send out, so just over 1uS/byte, the fastest you can go. Not sure if it's spdr or SPDR to at the start of a line, and nop has to be defined as an assembler call at the top of the sketch. Has been a couple years since I worked this out with Nick Gammon's help.

Also: the clock only runs during the 8 bit transfer.

Thank You!!!

If the clock stops right at the last bit transferred for each of the SPI.transfers, theoretically my method right now should work correct? because there should be no clock toggling when not sending data

If it doesnt I will look into the shift register solution you suggested

very much appreciated

@philipjfry

It is possible to pipeline the SPI code so that there is minimum delay between data. The trick is to load/store data during the transfer. Here is a link to the SPI device driver in Cosa. https://github.com/mikaelpatel/Cosa/blob/master/cores/cosa/Cosa/SPI.hh

As you will see the Cosa SPI has a somewhat different API to allow this.

Cheers!