Today I tried to used timer1 for triggering interrupts @20*60 Hz=1200 Hz. I followed the datasheet “15. 16-bit Timer/Counter1 with PWM” and inferred the following code:
// disable timer1 interrupts TIMSK1 = 0; // Mode 4, CTC using OCR1A TCCR1A = 1<<WGM12; // set prescaler to 1 TCCR1B = 1<<CS10; // Set OCR1A for running at 1200 Hz (because we have 20 discrete phases per period and want to have 60 Hz) OCR1A = (F_CPU / (60*20)) - 1; // enable match interrupts TIMSK1 = 1<<OCIE1A;
however ISR(TIMER1_COMPA_vect) gets triggered to slow. Using a frequency counter it appears that the ISR triggers every 65536 or 65535 CPU cycles. That is it looks as if it gets triggered when the timer reaches the 16bit overflow.
Has anyone a hint for me on what I am missing here?