Understand the purpose of a CLOCK INHIBIT pin on a 74HC165 PISO shift register

Hello everyone,

I am trying to understand the purpose of the clock inhibit in the 74HC165 shift register,

Here is the logic circuit according to the datasheet:

What I can see is the CLOCK INHIBIT line and CLOCK line is going to an OR gate,

When CLOCK INH is held low, the output of the OR gate behaves just like the clock. However, if CLOCK INH is held high, the output is always high no matter what the clock is doing, what is the point of doing this? howcome the 74HC595 SIPO register don't have this?

One theory I have this when the CLOCK INH is held high, this basically stops the heart beat to the S/R, it doesn't matter whether it is a constant high or low, the fact that we no longer have a positive edge going into the S/R, we basically turned it off, am I correct?

Thank you!

wingsuncheung2609:
What I can see is the CLOCK INHIBIT line and CLOCK line is going to an OR gate,

When CLOCK INH is held low, the output of the OR gate behaves just like the clock. However, if CLOCK INH is held high, the output is always high no matter what the clock is doing, what is the point of doing this?

howcome the 74HC595 SIPO register don't have this?

Correct.
Correct. A way to inhibit clocking.
Ask the designer of the 74HC595

You might have lots of shift registers all clocked from the same clock, in which case clock inhibit gives you a means to control which ones are clocked and which are not.

Also a means to power savings. CMOS uses energy when things change state.
How do you keep 8 shift registers from changing their outputs (and using energy) when they just need to hold their output state? Keep the clock from running.

Clock inhibit and enable are just opposite views on the same pin and functionality, with only opposite active signal levels.

Imagine you want to use the '165 for SPI input, an active high INH signal is equivalent to an active low SS signal, with CLK, MISO (Qh) and MOSI (SER) lines shared with other SPI shift registers. Eventually the SS signal also can be used for the LD signal to transfer the parallel input to the shift register before shifting starts.
Caveat: the Qh output can not be shared as is, deserves another gate for throughput to a shared MISO line only while SS/INH is low.

Output registers like '595 have slightly different requirements. New values have to become visible on the outputs only after all bits have been shifted in. Here SS is connected to the RCLK (latch) input so that after the SPI transfer is complete the shifted bits are copied into the output latches.

In the olden days, it was far more common to find free running clock signals in a circuit. With this IC function, you might not want it to shift all the time. So having an internal clock enable saves having to gate the clock externally (which would involve an extra logic IC, or part of one).

I get it now, thank you for everybody's input and time!