Hi!
I've been playing with unoptimized code and saw something I didn't understand:
Every assignment apparently takes a non-integer number of cycles and a boolean negation apparently takes zero cycles.
Oscilloscope screenshots:
The .ino code:
#pragma GCC optimize ("-O0")
#pragma GCC push_options
void setup() {
DDRB = 0xFF; //8 a 13 -> output
DDRD = 0x00; //0 a 7 -> input
PORTD = 0x80; //7 -> pullup
bool variavel_bool = false;
int variavel_int = 0x0000;
long variavel_long = 0x00000000;
unsigned variavel_unsigned = 0x0000;
float variavel_float = 0.0;
char variavel_char = '0';
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_bool = true;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_int = 0xF0F0;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_long = 0xF0F0F0F0;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_unsigned = 0xF0F0;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_float = 3.3;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_char = '1';
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_bool != variavel_bool;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_int += variavel_int;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_long += variavel_long;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_unsigned += variavel_unsigned;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_float += variavel_float;
PORTB = 0x00;
delay(50);
while(!(PIND & 0x80));
while(PIND & 0x80);
PORTB = 0xFF;
PORTB = 0x00;
PORTB = 0xFF;
variavel_char += variavel_char;
PORTB = 0x00;
//Serial.begin(300);
//Serial.println();
}
void loop() {}
#pragma GCC pop_options
The unoptimized output:
Disassembly of section .text:
00000000 <__vectors>:
0: 0c 94 34 00 jmp 0x68 ; 0x68 <__ctors_end>
4: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
8: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
c: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
10: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
14: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
18: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
1c: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
20: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
24: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
28: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
2c: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
30: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
34: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
38: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
3c: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
40: 0c 94 a0 00 jmp 0x140 ; 0x140 <__vector_16>
44: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
48: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
4c: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
50: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
54: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
58: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
5c: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
60: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
64: 0c 94 46 00 jmp 0x8c ; 0x8c <__bad_interrupt>
00000068 <__ctors_end>:
68: 11 24 eor r1, r1
6a: 1f be out 0x3f, r1 ; 63
6c: cf ef ldi r28, 0xFF ; 255
6e: d8 e0 ldi r29, 0x08 ; 8
70: de bf out 0x3e, r29 ; 62
72: cd bf out 0x3d, r28 ; 61
00000074 <__do_clear_bss>:
74: 21 e0 ldi r18, 0x01 ; 1
76: a0 e0 ldi r26, 0x00 ; 0
78: b1 e0 ldi r27, 0x01 ; 1
7a: 01 c0 rjmp .+2 ; 0x7e <.do_clear_bss_start>
0000007c <.do_clear_bss_loop>:
7c: 1d 92 st X+, r1
0000007e <.do_clear_bss_start>:
7e: a9 30 cpi r26, 0x09 ; 9
80: b2 07 cpc r27, r18
82: e1 f7 brne .-8 ; 0x7c <.do_clear_bss_loop>
84: 0e 94 5b 03 call 0x6b6 ; 0x6b6 <main>
88: 0c 94 67 04 jmp 0x8ce ; 0x8ce <_exit>
0000008c <__bad_interrupt>:
8c: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
00000090 <micros>:
return m;
}
unsigned long micros() {
unsigned long m;
uint8_t oldSREG = SREG, t;
90: 3f b7 in r19, 0x3f ; 63
cli();
92: f8 94 cli
m = timer0_overflow_count;
94: 80 91 05 01 lds r24, 0x0105 ; 0x800105 <timer0_overflow_count>
98: 90 91 06 01 lds r25, 0x0106 ; 0x800106 <timer0_overflow_count+0x1>
9c: a0 91 07 01 lds r26, 0x0107 ; 0x800107 <timer0_overflow_count+0x2>
a0: b0 91 08 01 lds r27, 0x0108 ; 0x800108 <timer0_overflow_count+0x3>
#if defined(TCNT0)
t = TCNT0;
a4: 26 b5 in r18, 0x26 ; 38
#else
#error TIMER 0 not defined
#endif
#ifdef TIFR0
if ((TIFR0 & _BV(TOV0)) && (t < 255))
a6: a8 9b sbis 0x15, 0 ; 21
a8: 05 c0 rjmp .+10 ; 0xb4 <micros+0x24>
aa: 2f 3f cpi r18, 0xFF ; 255
ac: 19 f0 breq .+6 ; 0xb4 <micros+0x24>
m++;
ae: 01 96 adiw r24, 0x01 ; 1
b0: a1 1d adc r26, r1
b2: b1 1d adc r27, r1
#else
if ((TIFR & _BV(TOV0)) && (t < 255))
m++;
#endif
SREG = oldSREG;
b4: 3f bf out 0x3f, r19 ; 63
return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond());
b6: ba 2f mov r27, r26
b8: a9 2f mov r26, r25
ba: 98 2f mov r25, r24
bc: 88 27 eor r24, r24
be: bc 01 movw r22, r24
c0: cd 01 movw r24, r26
c2: 62 0f add r22, r18
c4: 71 1d adc r23, r1
c6: 81 1d adc r24, r1
c8: 91 1d adc r25, r1
ca: 42 e0 ldi r20, 0x02 ; 2
cc: 66 0f add r22, r22
ce: 77 1f adc r23, r23
d0: 88 1f adc r24, r24
d2: 99 1f adc r25, r25
d4: 4a 95 dec r20
d6: d1 f7 brne .-12 ; 0xcc <micros+0x3c>
}
d8: 08 95 ret
000000da <delay>:
void delay(unsigned long ms)
{
da: 8f 92 push r8
dc: 9f 92 push r9
de: af 92 push r10
e0: bf 92 push r11
e2: cf 92 push r12
e4: df 92 push r13
e6: ef 92 push r14
e8: ff 92 push r15
ea: 6b 01 movw r12, r22
ec: 7c 01 movw r14, r24
uint32_t start = micros();
ee: 0e 94 48 00 call 0x90 ; 0x90 <micros>
f2: 4b 01 movw r8, r22
f4: 5c 01 movw r10, r24
while (ms > 0) {
yield();
while ( ms > 0 && (micros() - start) >= 1000) {
f6: c1 14 cp r12, r1
f8: d1 04 cpc r13, r1
fa: e1 04 cpc r14, r1
fc: f1 04 cpc r15, r1
fe: b9 f0 breq .+46 ; 0x12e <delay+0x54>
100: 0e 94 48 00 call 0x90 ; 0x90 <micros>
104: 68 19 sub r22, r8
106: 79 09 sbc r23, r9
108: 8a 09 sbc r24, r10
10a: 9b 09 sbc r25, r11
10c: 68 3e cpi r22, 0xE8 ; 232
10e: 73 40 sbci r23, 0x03 ; 3
110: 81 05 cpc r24, r1
112: 91 05 cpc r25, r1
114: 80 f3 brcs .-32 ; 0xf6 <delay+0x1c>
ms--;
116: 21 e0 ldi r18, 0x01 ; 1
118: c2 1a sub r12, r18
11a: d1 08 sbc r13, r1
11c: e1 08 sbc r14, r1
11e: f1 08 sbc r15, r1
start += 1000;
120: 88 ee ldi r24, 0xE8 ; 232
122: 88 0e add r8, r24
124: 83 e0 ldi r24, 0x03 ; 3
126: 98 1e adc r9, r24
128: a1 1c adc r10, r1
12a: b1 1c adc r11, r1
12c: e4 cf rjmp .-56 ; 0xf6 <delay+0x1c>
}
}
}
12e: ff 90 pop r15
130: ef 90 pop r14
132: df 90 pop r13
134: cf 90 pop r12
136: bf 90 pop r11
138: af 90 pop r10
13a: 9f 90 pop r9
13c: 8f 90 pop r8
13e: 08 95 ret
00000140 <__vector_16>:
#if defined(TIM0_OVF_vect)
ISR(TIM0_OVF_vect)
#else
ISR(TIMER0_OVF_vect)
#endif
{
140: 1f 92 push r1
142: 0f 92 push r0
144: 0f b6 in r0, 0x3f ; 63
146: 0f 92 push r0
148: 11 24 eor r1, r1
14a: 2f 93 push r18
14c: 3f 93 push r19
14e: 8f 93 push r24
150: 9f 93 push r25
152: af 93 push r26
154: bf 93 push r27
// copy these to local variables so they can be stored in registers
// (volatile variables must be read from memory on every access)
unsigned long m = timer0_millis;
156: 80 91 01 01 lds r24, 0x0101 ; 0x800101 <timer0_millis>
15a: 90 91 02 01 lds r25, 0x0102 ; 0x800102 <timer0_millis+0x1>
15e: a0 91 03 01 lds r26, 0x0103 ; 0x800103 <timer0_millis+0x2>
162: b0 91 04 01 lds r27, 0x0104 ; 0x800104 <timer0_millis+0x3>
unsigned char f = timer0_fract;
166: 30 91 00 01 lds r19, 0x0100 ; 0x800100 <_edata>
m += MILLIS_INC;
f += FRACT_INC;
16a: 23 e0 ldi r18, 0x03 ; 3
16c: 23 0f add r18, r19
if (f >= FRACT_MAX) {
16e: 2d 37 cpi r18, 0x7D ; 125
170: 58 f5 brcc .+86 ; 0x1c8 <__vector_16+0x88>
// copy these to local variables so they can be stored in registers
// (volatile variables must be read from memory on every access)
unsigned long m = timer0_millis;
unsigned char f = timer0_fract;
m += MILLIS_INC;
172: 01 96 adiw r24, 0x01 ; 1
174: a1 1d adc r26, r1
176: b1 1d adc r27, r1
if (f >= FRACT_MAX) {
f -= FRACT_MAX;
m += 1;
}
timer0_fract = f;
178: 20 93 00 01 sts 0x0100, r18 ; 0x800100 <_edata>
timer0_millis = m;
17c: 80 93 01 01 sts 0x0101, r24 ; 0x800101 <timer0_millis>
180: 90 93 02 01 sts 0x0102, r25 ; 0x800102 <timer0_millis+0x1>
184: a0 93 03 01 sts 0x0103, r26 ; 0x800103 <timer0_millis+0x2>
188: b0 93 04 01 sts 0x0104, r27 ; 0x800104 <timer0_millis+0x3>
timer0_overflow_count++;
18c: 80 91 05 01 lds r24, 0x0105 ; 0x800105 <timer0_overflow_count>
190: 90 91 06 01 lds r25, 0x0106 ; 0x800106 <timer0_overflow_count+0x1>
194: a0 91 07 01 lds r26, 0x0107 ; 0x800107 <timer0_overflow_count+0x2>
198: b0 91 08 01 lds r27, 0x0108 ; 0x800108 <timer0_overflow_count+0x3>
19c: 01 96 adiw r24, 0x01 ; 1
19e: a1 1d adc r26, r1
1a0: b1 1d adc r27, r1
1a2: 80 93 05 01 sts 0x0105, r24 ; 0x800105 <timer0_overflow_count>
1a6: 90 93 06 01 sts 0x0106, r25 ; 0x800106 <timer0_overflow_count+0x1>
1aa: a0 93 07 01 sts 0x0107, r26 ; 0x800107 <timer0_overflow_count+0x2>
1ae: b0 93 08 01 sts 0x0108, r27 ; 0x800108 <timer0_overflow_count+0x3>
}
1b2: bf 91 pop r27
1b4: af 91 pop r26
1b6: 9f 91 pop r25
1b8: 8f 91 pop r24
1ba: 3f 91 pop r19
1bc: 2f 91 pop r18
1be: 0f 90 pop r0
1c0: 0f be out 0x3f, r0 ; 63
1c2: 0f 90 pop r0
1c4: 1f 90 pop r1
1c6: 18 95 reti
unsigned char f = timer0_fract;
m += MILLIS_INC;
f += FRACT_INC;
if (f >= FRACT_MAX) {
f -= FRACT_MAX;
1c8: 26 e8 ldi r18, 0x86 ; 134
1ca: 23 0f add r18, r19
m += 1;
1cc: 02 96 adiw r24, 0x02 ; 2
1ce: a1 1d adc r26, r1
1d0: b1 1d adc r27, r1
1d2: d2 cf rjmp .-92 ; 0x178 <__vector_16+0x38>
000001d4 <loop>:
1d4: cf 93 push r28
1d6: df 93 push r29
1d8: cd b7 in r28, 0x3d ; 61
1da: de b7 in r29, 0x3e ; 62
1dc: df 91 pop r29
1de: cf 91 pop r28
1e0: 08 95 ret
000001e2 <setup>:
1e2: cf 93 push r28
1e4: df 93 push r29
1e6: cd b7 in r28, 0x3d ; 61
1e8: de b7 in r29, 0x3e ; 62
1ea: 2e 97 sbiw r28, 0x0e ; 14
1ec: 0f b6 in r0, 0x3f ; 63
1ee: f8 94 cli
1f0: de bf out 0x3e, r29 ; 62
1f2: 0f be out 0x3f, r0 ; 63
1f4: cd bf out 0x3d, r28 ; 61
1f6: 84 e2 ldi r24, 0x24 ; 36
1f8: 90 e0 ldi r25, 0x00 ; 0
1fa: 2f ef ldi r18, 0xFF ; 255
1fc: fc 01 movw r30, r24
1fe: 20 83 st Z, r18
200: 8a e2 ldi r24, 0x2A ; 42
202: 90 e0 ldi r25, 0x00 ; 0
204: fc 01 movw r30, r24
206: 10 82 st Z, r1
208: 8b e2 ldi r24, 0x2B ; 43
20a: 90 e0 ldi r25, 0x00 ; 0
20c: 20 e8 ldi r18, 0x80 ; 128
20e: fc 01 movw r30, r24
210: 20 83 st Z, r18
212: 19 82 std Y+1, r1 ; 0x01
214: 1b 82 std Y+3, r1 ; 0x03
216: 1a 82 std Y+2, r1 ; 0x02
218: 1c 82 std Y+4, r1 ; 0x04
21a: 1d 82 std Y+5, r1 ; 0x05
21c: 1e 82 std Y+6, r1 ; 0x06
21e: 1f 82 std Y+7, r1 ; 0x07
220: 19 86 std Y+9, r1 ; 0x09
222: 18 86 std Y+8, r1 ; 0x08
224: 1a 86 std Y+10, r1 ; 0x0a
226: 1b 86 std Y+11, r1 ; 0x0b
228: 1c 86 std Y+12, r1 ; 0x0c
22a: 1d 86 std Y+13, r1 ; 0x0d
22c: 80 e3 ldi r24, 0x30 ; 48
22e: 8e 87 std Y+14, r24 ; 0x0e
230: 89 e2 ldi r24, 0x29 ; 41
232: 90 e0 ldi r25, 0x00 ; 0
234: fc 01 movw r30, r24
236: 80 81 ld r24, Z
238: 88 1f adc r24, r24
23a: 88 27 eor r24, r24
23c: 88 1f adc r24, r24
23e: 88 23 and r24, r24
240: b9 f7 brne .-18 ; 0x230 <setup+0x4e>
242: 85 e2 ldi r24, 0x25 ; 37
244: 90 e0 ldi r25, 0x00 ; 0
246: 2f ef ldi r18, 0xFF ; 255
248: fc 01 movw r30, r24
24a: 20 83 st Z, r18
24c: 85 e2 ldi r24, 0x25 ; 37
24e: 90 e0 ldi r25, 0x00 ; 0
250: fc 01 movw r30, r24
252: 10 82 st Z, r1
254: 85 e2 ldi r24, 0x25 ; 37
256: 90 e0 ldi r25, 0x00 ; 0
258: 2f ef ldi r18, 0xFF ; 255
25a: fc 01 movw r30, r24
25c: 20 83 st Z, r18
25e: 81 e0 ldi r24, 0x01 ; 1
260: 89 83 std Y+1, r24 ; 0x01
262: 85 e2 ldi r24, 0x25 ; 37
264: 90 e0 ldi r25, 0x00 ; 0
266: fc 01 movw r30, r24
268: 10 82 st Z, r1
26a: 62 e3 ldi r22, 0x32 ; 50
26c: 70 e0 ldi r23, 0x00 ; 0
26e: 80 e0 ldi r24, 0x00 ; 0
270: 90 e0 ldi r25, 0x00 ; 0
272: 0e 94 6d 00 call 0xda ; 0xda <delay>
276: 89 e2 ldi r24, 0x29 ; 41
278: 90 e0 ldi r25, 0x00 ; 0
27a: fc 01 movw r30, r24
27c: 80 81 ld r24, Z
27e: 80 95 com r24
280: 88 1f adc r24, r24
282: 88 27 eor r24, r24
284: 88 1f adc r24, r24
286: 88 23 and r24, r24
288: b1 f7 brne .-20 ; 0x276 <setup+0x94>
28a: 89 e2 ldi r24, 0x29 ; 41
28c: 90 e0 ldi r25, 0x00 ; 0
28e: fc 01 movw r30, r24
290: 80 81 ld r24, Z
292: 88 1f adc r24, r24
294: 88 27 eor r24, r24
296: 88 1f adc r24, r24
298: 88 23 and r24, r24
29a: b9 f7 brne .-18 ; 0x28a <setup+0xa8>
29c: 85 e2 ldi r24, 0x25 ; 37
29e: 90 e0 ldi r25, 0x00 ; 0
2a0: 2f ef ldi r18, 0xFF ; 255
2a2: fc 01 movw r30, r24
2a4: 20 83 st Z, r18
2a6: 85 e2 ldi r24, 0x25 ; 37
2a8: 90 e0 ldi r25, 0x00 ; 0
2aa: fc 01 movw r30, r24
2ac: 10 82 st Z, r1
2ae: 85 e2 ldi r24, 0x25 ; 37
2b0: 90 e0 ldi r25, 0x00 ; 0
2b2: 2f ef ldi r18, 0xFF ; 255
2b4: fc 01 movw r30, r24
2b6: 20 83 st Z, r18
2b8: 80 ef ldi r24, 0xF0 ; 240
2ba: 90 ef ldi r25, 0xF0 ; 240
2bc: 9b 83 std Y+3, r25 ; 0x03
2be: 8a 83 std Y+2, r24 ; 0x02
2c0: 85 e2 ldi r24, 0x25 ; 37
2c2: 90 e0 ldi r25, 0x00 ; 0
2c4: fc 01 movw r30, r24
2c6: 10 82 st Z, r1
2c8: 62 e3 ldi r22, 0x32 ; 50
2ca: 70 e0 ldi r23, 0x00 ; 0
2cc: 80 e0 ldi r24, 0x00 ; 0
2ce: 90 e0 ldi r25, 0x00 ; 0
2d0: 0e 94 6d 00 call 0xda ; 0xda <delay>
2d4: 89 e2 ldi r24, 0x29 ; 41
2d6: 90 e0 ldi r25, 0x00 ; 0
2d8: fc 01 movw r30, r24
2da: 80 81 ld r24, Z
2dc: 80 95 com r24
2de: 88 1f adc r24, r24
2e0: 88 27 eor r24, r24
2e2: 88 1f adc r24, r24
2e4: 88 23 and r24, r24
2e6: b1 f7 brne .-20 ; 0x2d4 <setup+0xf2>
2e8: 89 e2 ldi r24, 0x29 ; 41
2ea: 90 e0 ldi r25, 0x00 ; 0
2ec: fc 01 movw r30, r24
2ee: 80 81 ld r24, Z
2f0: 88 1f adc r24, r24
2f2: 88 27 eor r24, r24
2f4: 88 1f adc r24, r24
2f6: 88 23 and r24, r24
2f8: b9 f7 brne .-18 ; 0x2e8 <setup+0x106>
2fa: 85 e2 ldi r24, 0x25 ; 37
2fc: 90 e0 ldi r25, 0x00 ; 0
2fe: 2f ef ldi r18, 0xFF ; 255
300: fc 01 movw r30, r24
302: 20 83 st Z, r18
304: 85 e2 ldi r24, 0x25 ; 37
306: 90 e0 ldi r25, 0x00 ; 0
308: fc 01 movw r30, r24
30a: 10 82 st Z, r1
30c: 85 e2 ldi r24, 0x25 ; 37
30e: 90 e0 ldi r25, 0x00 ; 0
310: 2f ef ldi r18, 0xFF ; 255
312: fc 01 movw r30, r24
314: 20 83 st Z, r18
316: 80 ef ldi r24, 0xF0 ; 240
318: 90 ef ldi r25, 0xF0 ; 240
31a: dc 01 movw r26, r24
31c: 8c 83 std Y+4, r24 ; 0x04
31e: 9d 83 std Y+5, r25 ; 0x05
320: ae 83 std Y+6, r26 ; 0x06
322: bf 83 std Y+7, r27 ; 0x07
324: 85 e2 ldi r24, 0x25 ; 37
326: 90 e0 ldi r25, 0x00 ; 0
328: fc 01 movw r30, r24
32a: 10 82 st Z, r1
32c: 62 e3 ldi r22, 0x32 ; 50
32e: 70 e0 ldi r23, 0x00 ; 0
330: 80 e0 ldi r24, 0x00 ; 0
332: 90 e0 ldi r25, 0x00 ; 0
334: 0e 94 6d 00 call 0xda ; 0xda <delay>
338: 89 e2 ldi r24, 0x29 ; 41
33a: 90 e0 ldi r25, 0x00 ; 0
33c: fc 01 movw r30, r24
33e: 80 81 ld r24, Z
340: 80 95 com r24
342: 88 1f adc r24, r24
344: 88 27 eor r24, r24
346: 88 1f adc r24, r24
348: 88 23 and r24, r24
34a: b1 f7 brne .-20 ; 0x338 <setup+0x156>
34c: 89 e2 ldi r24, 0x29 ; 41
34e: 90 e0 ldi r25, 0x00 ; 0
350: fc 01 movw r30, r24
352: 80 81 ld r24, Z
354: 88 1f adc r24, r24
356: 88 27 eor r24, r24
358: 88 1f adc r24, r24
35a: 88 23 and r24, r24
35c: b9 f7 brne .-18 ; 0x34c <setup+0x16a>
35e: 85 e2 ldi r24, 0x25 ; 37
360: 90 e0 ldi r25, 0x00 ; 0
362: 2f ef ldi r18, 0xFF ; 255
364: fc 01 movw r30, r24
366: 20 83 st Z, r18
368: 85 e2 ldi r24, 0x25 ; 37
36a: 90 e0 ldi r25, 0x00 ; 0
36c: fc 01 movw r30, r24
36e: 10 82 st Z, r1
370: 85 e2 ldi r24, 0x25 ; 37
372: 90 e0 ldi r25, 0x00 ; 0
374: 2f ef ldi r18, 0xFF ; 255
376: fc 01 movw r30, r24
378: 20 83 st Z, r18
37a: 80 ef ldi r24, 0xF0 ; 240
37c: 90 ef ldi r25, 0xF0 ; 240
37e: 99 87 std Y+9, r25 ; 0x09
380: 88 87 std Y+8, r24 ; 0x08
382: 85 e2 ldi r24, 0x25 ; 37
384: 90 e0 ldi r25, 0x00 ; 0
386: fc 01 movw r30, r24
388: 10 82 st Z, r1
38a: 62 e3 ldi r22, 0x32 ; 50
38c: 70 e0 ldi r23, 0x00 ; 0
38e: 80 e0 ldi r24, 0x00 ; 0
390: 90 e0 ldi r25, 0x00 ; 0
392: 0e 94 6d 00 call 0xda ; 0xda <delay>
396: 89 e2 ldi r24, 0x29 ; 41
398: 90 e0 ldi r25, 0x00 ; 0
39a: fc 01 movw r30, r24
39c: 80 81 ld r24, Z
39e: 80 95 com r24
3a0: 88 1f adc r24, r24
3a2: 88 27 eor r24, r24
3a4: 88 1f adc r24, r24
3a6: 88 23 and r24, r24
3a8: b1 f7 brne .-20 ; 0x396 <setup+0x1b4>
3aa: 89 e2 ldi r24, 0x29 ; 41
3ac: 90 e0 ldi r25, 0x00 ; 0
3ae: fc 01 movw r30, r24
3b0: 80 81 ld r24, Z
3b2: 88 1f adc r24, r24
3b4: 88 27 eor r24, r24
3b6: 88 1f adc r24, r24
3b8: 88 23 and r24, r24
3ba: b9 f7 brne .-18 ; 0x3aa <setup+0x1c8>
3bc: 85 e2 ldi r24, 0x25 ; 37
3be: 90 e0 ldi r25, 0x00 ; 0
3c0: 2f ef ldi r18, 0xFF ; 255
3c2: fc 01 movw r30, r24
3c4: 20 83 st Z, r18
3c6: 85 e2 ldi r24, 0x25 ; 37
3c8: 90 e0 ldi r25, 0x00 ; 0
3ca: fc 01 movw r30, r24
3cc: 10 82 st Z, r1
3ce: 85 e2 ldi r24, 0x25 ; 37
3d0: 90 e0 ldi r25, 0x00 ; 0
3d2: 2f ef ldi r18, 0xFF ; 255
3d4: fc 01 movw r30, r24
3d6: 20 83 st Z, r18
3d8: 83 e3 ldi r24, 0x33 ; 51
3da: 93 e3 ldi r25, 0x33 ; 51
3dc: a3 e5 ldi r26, 0x53 ; 83
3de: b0 e4 ldi r27, 0x40 ; 64
3e0: 8a 87 std Y+10, r24 ; 0x0a
3e2: 9b 87 std Y+11, r25 ; 0x0b
3e4: ac 87 std Y+12, r26 ; 0x0c
3e6: bd 87 std Y+13, r27 ; 0x0d
3e8: 85 e2 ldi r24, 0x25 ; 37
3ea: 90 e0 ldi r25, 0x00 ; 0
3ec: fc 01 movw r30, r24
3ee: 10 82 st Z, r1
3f0: 62 e3 ldi r22, 0x32 ; 50
3f2: 70 e0 ldi r23, 0x00 ; 0
3f4: 80 e0 ldi r24, 0x00 ; 0
3f6: 90 e0 ldi r25, 0x00 ; 0
3f8: 0e 94 6d 00 call 0xda ; 0xda <delay>
3fc: 89 e2 ldi r24, 0x29 ; 41
3fe: 90 e0 ldi r25, 0x00 ; 0
400: fc 01 movw r30, r24
402: 80 81 ld r24, Z
404: 80 95 com r24
406: 88 1f adc r24, r24
408: 88 27 eor r24, r24
40a: 88 1f adc r24, r24
40c: 88 23 and r24, r24
40e: b1 f7 brne .-20 ; 0x3fc <setup+0x21a>
410: 89 e2 ldi r24, 0x29 ; 41
412: 90 e0 ldi r25, 0x00 ; 0
414: fc 01 movw r30, r24
416: 80 81 ld r24, Z
418: 88 1f adc r24, r24
41a: 88 27 eor r24, r24
41c: 88 1f adc r24, r24
41e: 88 23 and r24, r24
420: b9 f7 brne .-18 ; 0x410 <__LOCK_REGION_LENGTH__+0x10>
422: 85 e2 ldi r24, 0x25 ; 37
424: 90 e0 ldi r25, 0x00 ; 0
426: 2f ef ldi r18, 0xFF ; 255
428: fc 01 movw r30, r24
42a: 20 83 st Z, r18
42c: 85 e2 ldi r24, 0x25 ; 37
42e: 90 e0 ldi r25, 0x00 ; 0
430: fc 01 movw r30, r24
432: 10 82 st Z, r1
434: 85 e2 ldi r24, 0x25 ; 37
436: 90 e0 ldi r25, 0x00 ; 0
438: 2f ef ldi r18, 0xFF ; 255
43a: fc 01 movw r30, r24
43c: 20 83 st Z, r18
43e: 81 e3 ldi r24, 0x31 ; 49
440: 8e 87 std Y+14, r24 ; 0x0e
442: 85 e2 ldi r24, 0x25 ; 37
444: 90 e0 ldi r25, 0x00 ; 0
446: fc 01 movw r30, r24
448: 10 82 st Z, r1
44a: 62 e3 ldi r22, 0x32 ; 50
44c: 70 e0 ldi r23, 0x00 ; 0
44e: 80 e0 ldi r24, 0x00 ; 0
450: 90 e0 ldi r25, 0x00 ; 0
452: 0e 94 6d 00 call 0xda ; 0xda <delay>
456: 89 e2 ldi r24, 0x29 ; 41
458: 90 e0 ldi r25, 0x00 ; 0
45a: fc 01 movw r30, r24
45c: 80 81 ld r24, Z
45e: 80 95 com r24
460: 88 1f adc r24, r24
462: 88 27 eor r24, r24
464: 88 1f adc r24, r24
466: 88 23 and r24, r24
468: b1 f7 brne .-20 ; 0x456 <__LOCK_REGION_LENGTH__+0x56>
46a: 89 e2 ldi r24, 0x29 ; 41
46c: 90 e0 ldi r25, 0x00 ; 0
46e: fc 01 movw r30, r24
470: 80 81 ld r24, Z
472: 88 1f adc r24, r24
474: 88 27 eor r24, r24
476: 88 1f adc r24, r24
478: 88 23 and r24, r24
47a: b9 f7 brne .-18 ; 0x46a <__LOCK_REGION_LENGTH__+0x6a>
47c: 85 e2 ldi r24, 0x25 ; 37
47e: 90 e0 ldi r25, 0x00 ; 0
480: 2f ef ldi r18, 0xFF ; 255
482: fc 01 movw r30, r24
484: 20 83 st Z, r18
486: 85 e2 ldi r24, 0x25 ; 37
488: 90 e0 ldi r25, 0x00 ; 0
48a: fc 01 movw r30, r24
48c: 10 82 st Z, r1
48e: 85 e2 ldi r24, 0x25 ; 37
490: 90 e0 ldi r25, 0x00 ; 0
492: 2f ef ldi r18, 0xFF ; 255
494: fc 01 movw r30, r24
496: 20 83 st Z, r18
498: 85 e2 ldi r24, 0x25 ; 37
49a: 90 e0 ldi r25, 0x00 ; 0
49c: fc 01 movw r30, r24
49e: 10 82 st Z, r1
4a0: 62 e3 ldi r22, 0x32 ; 50
4a2: 70 e0 ldi r23, 0x00 ; 0
4a4: 80 e0 ldi r24, 0x00 ; 0
4a6: 90 e0 ldi r25, 0x00 ; 0
4a8: 0e 94 6d 00 call 0xda ; 0xda <delay>
4ac: 89 e2 ldi r24, 0x29 ; 41
4ae: 90 e0 ldi r25, 0x00 ; 0
4b0: fc 01 movw r30, r24
4b2: 80 81 ld r24, Z
4b4: 80 95 com r24
4b6: 88 1f adc r24, r24
4b8: 88 27 eor r24, r24
4ba: 88 1f adc r24, r24
4bc: 88 23 and r24, r24
4be: b1 f7 brne .-20 ; 0x4ac <__LOCK_REGION_LENGTH__+0xac>
4c0: 89 e2 ldi r24, 0x29 ; 41
4c2: 90 e0 ldi r25, 0x00 ; 0
4c4: fc 01 movw r30, r24
4c6: 80 81 ld r24, Z
4c8: 88 1f adc r24, r24
4ca: 88 27 eor r24, r24
4cc: 88 1f adc r24, r24
4ce: 88 23 and r24, r24
4d0: b9 f7 brne .-18 ; 0x4c0 <__LOCK_REGION_LENGTH__+0xc0>
4d2: 85 e2 ldi r24, 0x25 ; 37
4d4: 90 e0 ldi r25, 0x00 ; 0
4d6: 2f ef ldi r18, 0xFF ; 255
4d8: fc 01 movw r30, r24
4da: 20 83 st Z, r18
4dc: 85 e2 ldi r24, 0x25 ; 37
4de: 90 e0 ldi r25, 0x00 ; 0
4e0: fc 01 movw r30, r24
4e2: 10 82 st Z, r1
4e4: 85 e2 ldi r24, 0x25 ; 37
4e6: 90 e0 ldi r25, 0x00 ; 0
4e8: 2f ef ldi r18, 0xFF ; 255
4ea: fc 01 movw r30, r24
4ec: 20 83 st Z, r18
4ee: 8a 81 ldd r24, Y+2 ; 0x02
4f0: 9b 81 ldd r25, Y+3 ; 0x03
4f2: 88 0f add r24, r24
4f4: 99 1f adc r25, r25
4f6: 9b 83 std Y+3, r25 ; 0x03
4f8: 8a 83 std Y+2, r24 ; 0x02
4fa: 85 e2 ldi r24, 0x25 ; 37
4fc: 90 e0 ldi r25, 0x00 ; 0
4fe: fc 01 movw r30, r24
500: 10 82 st Z, r1
502: 62 e3 ldi r22, 0x32 ; 50
504: 70 e0 ldi r23, 0x00 ; 0
506: 80 e0 ldi r24, 0x00 ; 0
508: 90 e0 ldi r25, 0x00 ; 0
50a: 0e 94 6d 00 call 0xda ; 0xda <delay>
50e: 89 e2 ldi r24, 0x29 ; 41
510: 90 e0 ldi r25, 0x00 ; 0
512: fc 01 movw r30, r24
514: 80 81 ld r24, Z
516: 80 95 com r24
518: 88 1f adc r24, r24
51a: 88 27 eor r24, r24
51c: 88 1f adc r24, r24
51e: 88 23 and r24, r24
520: b1 f7 brne .-20 ; 0x50e <__LOCK_REGION_LENGTH__+0x10e>
522: 89 e2 ldi r24, 0x29 ; 41
524: 90 e0 ldi r25, 0x00 ; 0
526: fc 01 movw r30, r24
528: 80 81 ld r24, Z
52a: 88 1f adc r24, r24
52c: 88 27 eor r24, r24
52e: 88 1f adc r24, r24
530: 88 23 and r24, r24
532: b9 f7 brne .-18 ; 0x522 <__LOCK_REGION_LENGTH__+0x122>
534: 85 e2 ldi r24, 0x25 ; 37
536: 90 e0 ldi r25, 0x00 ; 0
538: 2f ef ldi r18, 0xFF ; 255
53a: fc 01 movw r30, r24
53c: 20 83 st Z, r18
53e: 85 e2 ldi r24, 0x25 ; 37
540: 90 e0 ldi r25, 0x00 ; 0
542: fc 01 movw r30, r24
544: 10 82 st Z, r1
546: 85 e2 ldi r24, 0x25 ; 37
548: 90 e0 ldi r25, 0x00 ; 0
54a: 2f ef ldi r18, 0xFF ; 255
54c: fc 01 movw r30, r24
54e: 20 83 st Z, r18
550: 8c 81 ldd r24, Y+4 ; 0x04
552: 9d 81 ldd r25, Y+5 ; 0x05
554: ae 81 ldd r26, Y+6 ; 0x06
556: bf 81 ldd r27, Y+7 ; 0x07
558: 88 0f add r24, r24
55a: 99 1f adc r25, r25
55c: aa 1f adc r26, r26
55e: bb 1f adc r27, r27
560: 8c 83 std Y+4, r24 ; 0x04
562: 9d 83 std Y+5, r25 ; 0x05
564: ae 83 std Y+6, r26 ; 0x06
566: bf 83 std Y+7, r27 ; 0x07
568: 85 e2 ldi r24, 0x25 ; 37
56a: 90 e0 ldi r25, 0x00 ; 0
56c: fc 01 movw r30, r24
56e: 10 82 st Z, r1
570: 62 e3 ldi r22, 0x32 ; 50
572: 70 e0 ldi r23, 0x00 ; 0
574: 80 e0 ldi r24, 0x00 ; 0
576: 90 e0 ldi r25, 0x00 ; 0
578: 0e 94 6d 00 call 0xda ; 0xda <delay>
57c: 89 e2 ldi r24, 0x29 ; 41
57e: 90 e0 ldi r25, 0x00 ; 0
580: fc 01 movw r30, r24
582: 80 81 ld r24, Z
584: 80 95 com r24
586: 88 1f adc r24, r24
588: 88 27 eor r24, r24
58a: 88 1f adc r24, r24
58c: 88 23 and r24, r24
58e: b1 f7 brne .-20 ; 0x57c <__LOCK_REGION_LENGTH__+0x17c>
590: 89 e2 ldi r24, 0x29 ; 41
592: 90 e0 ldi r25, 0x00 ; 0
594: fc 01 movw r30, r24
596: 80 81 ld r24, Z
598: 88 1f adc r24, r24
59a: 88 27 eor r24, r24
59c: 88 1f adc r24, r24
59e: 88 23 and r24, r24
5a0: b9 f7 brne .-18 ; 0x590 <__LOCK_REGION_LENGTH__+0x190>
5a2: 85 e2 ldi r24, 0x25 ; 37
5a4: 90 e0 ldi r25, 0x00 ; 0
5a6: 2f ef ldi r18, 0xFF ; 255
5a8: fc 01 movw r30, r24
5aa: 20 83 st Z, r18
5ac: 85 e2 ldi r24, 0x25 ; 37
5ae: 90 e0 ldi r25, 0x00 ; 0
5b0: fc 01 movw r30, r24
5b2: 10 82 st Z, r1
5b4: 85 e2 ldi r24, 0x25 ; 37
5b6: 90 e0 ldi r25, 0x00 ; 0
5b8: 2f ef ldi r18, 0xFF ; 255
5ba: fc 01 movw r30, r24
5bc: 20 83 st Z, r18
5be: 88 85 ldd r24, Y+8 ; 0x08
5c0: 99 85 ldd r25, Y+9 ; 0x09
5c2: 88 0f add r24, r24
5c4: 99 1f adc r25, r25
5c6: 99 87 std Y+9, r25 ; 0x09
5c8: 88 87 std Y+8, r24 ; 0x08
5ca: 85 e2 ldi r24, 0x25 ; 37
5cc: 90 e0 ldi r25, 0x00 ; 0
5ce: fc 01 movw r30, r24
5d0: 10 82 st Z, r1
5d2: 62 e3 ldi r22, 0x32 ; 50
5d4: 70 e0 ldi r23, 0x00 ; 0
5d6: 80 e0 ldi r24, 0x00 ; 0
5d8: 90 e0 ldi r25, 0x00 ; 0
5da: 0e 94 6d 00 call 0xda ; 0xda <delay>
5de: 89 e2 ldi r24, 0x29 ; 41
5e0: 90 e0 ldi r25, 0x00 ; 0
5e2: fc 01 movw r30, r24
5e4: 80 81 ld r24, Z
5e6: 80 95 com r24
5e8: 88 1f adc r24, r24
5ea: 88 27 eor r24, r24
5ec: 88 1f adc r24, r24
5ee: 88 23 and r24, r24
5f0: b1 f7 brne .-20 ; 0x5de <__LOCK_REGION_LENGTH__+0x1de>
5f2: 89 e2 ldi r24, 0x29 ; 41
5f4: 90 e0 ldi r25, 0x00 ; 0
5f6: fc 01 movw r30, r24
5f8: 80 81 ld r24, Z
5fa: 88 1f adc r24, r24
5fc: 88 27 eor r24, r24
5fe: 88 1f adc r24, r24
600: 88 23 and r24, r24
602: b9 f7 brne .-18 ; 0x5f2 <__LOCK_REGION_LENGTH__+0x1f2>
604: 85 e2 ldi r24, 0x25 ; 37
606: 90 e0 ldi r25, 0x00 ; 0
608: 2f ef ldi r18, 0xFF ; 255
60a: fc 01 movw r30, r24
60c: 20 83 st Z, r18
60e: 85 e2 ldi r24, 0x25 ; 37
610: 90 e0 ldi r25, 0x00 ; 0
612: fc 01 movw r30, r24
614: 10 82 st Z, r1
616: 85 e2 ldi r24, 0x25 ; 37
618: 90 e0 ldi r25, 0x00 ; 0
61a: 2f ef ldi r18, 0xFF ; 255
61c: fc 01 movw r30, r24
61e: 20 83 st Z, r18
620: 8a 85 ldd r24, Y+10 ; 0x0a
622: 9b 85 ldd r25, Y+11 ; 0x0b
624: ac 85 ldd r26, Y+12 ; 0x0c
626: bd 85 ldd r27, Y+13 ; 0x0d
628: 9c 01 movw r18, r24
62a: ad 01 movw r20, r26
62c: bc 01 movw r22, r24
62e: cd 01 movw r24, r26
630: 0e 94 aa 03 call 0x754 ; 0x754 <__addsf3>
634: dc 01 movw r26, r24
636: cb 01 movw r24, r22
638: 8a 87 std Y+10, r24 ; 0x0a
63a: 9b 87 std Y+11, r25 ; 0x0b
63c: ac 87 std Y+12, r26 ; 0x0c
63e: bd 87 std Y+13, r27 ; 0x0d
640: 85 e2 ldi r24, 0x25 ; 37
642: 90 e0 ldi r25, 0x00 ; 0
644: fc 01 movw r30, r24
646: 10 82 st Z, r1
648: 62 e3 ldi r22, 0x32 ; 50
64a: 70 e0 ldi r23, 0x00 ; 0
64c: 80 e0 ldi r24, 0x00 ; 0
64e: 90 e0 ldi r25, 0x00 ; 0
650: 0e 94 6d 00 call 0xda ; 0xda <delay>
654: 89 e2 ldi r24, 0x29 ; 41
656: 90 e0 ldi r25, 0x00 ; 0
658: fc 01 movw r30, r24
65a: 80 81 ld r24, Z
65c: 80 95 com r24
65e: 88 1f adc r24, r24
660: 88 27 eor r24, r24
662: 88 1f adc r24, r24
664: 88 23 and r24, r24
666: b1 f7 brne .-20 ; 0x654 <__LOCK_REGION_LENGTH__+0x254>
668: 89 e2 ldi r24, 0x29 ; 41
66a: 90 e0 ldi r25, 0x00 ; 0
66c: fc 01 movw r30, r24
66e: 80 81 ld r24, Z
670: 88 1f adc r24, r24
672: 88 27 eor r24, r24
674: 88 1f adc r24, r24
676: 88 23 and r24, r24
678: b9 f7 brne .-18 ; 0x668 <__LOCK_REGION_LENGTH__+0x268>
67a: 85 e2 ldi r24, 0x25 ; 37
67c: 90 e0 ldi r25, 0x00 ; 0
67e: 2f ef ldi r18, 0xFF ; 255
680: fc 01 movw r30, r24
682: 20 83 st Z, r18
684: 85 e2 ldi r24, 0x25 ; 37
686: 90 e0 ldi r25, 0x00 ; 0
688: fc 01 movw r30, r24
68a: 10 82 st Z, r1
68c: 85 e2 ldi r24, 0x25 ; 37
68e: 90 e0 ldi r25, 0x00 ; 0
690: 2f ef ldi r18, 0xFF ; 255
692: fc 01 movw r30, r24
694: 20 83 st Z, r18
696: 8e 85 ldd r24, Y+14 ; 0x0e
698: 88 0f add r24, r24
69a: 8e 87 std Y+14, r24 ; 0x0e
69c: 85 e2 ldi r24, 0x25 ; 37
69e: 90 e0 ldi r25, 0x00 ; 0
6a0: fc 01 movw r30, r24
6a2: 10 82 st Z, r1
6a4: 2e 96 adiw r28, 0x0e ; 14
6a6: 0f b6 in r0, 0x3f ; 63
6a8: f8 94 cli
6aa: de bf out 0x3e, r29 ; 62
6ac: 0f be out 0x3f, r0 ; 63
6ae: cd bf out 0x3d, r28 ; 61
6b0: df 91 pop r29
6b2: cf 91 pop r28
6b4: 08 95 ret
000006b6 <main>:
void init()
{
// this needs to be called before setup() or some functions won't
// work there
sei();
6b6: 78 94 sei
// on the ATmega168, timer 0 is also used for fast hardware pwm
// (using phase-correct PWM would mean that timer 0 overflowed half as often
// resulting in different millis() behavior on the ATmega8 and ATmega168)
#if defined(TCCR0A) && defined(WGM01)
sbi(TCCR0A, WGM01);
6b8: 84 b5 in r24, 0x24 ; 36
6ba: 82 60 ori r24, 0x02 ; 2
6bc: 84 bd out 0x24, r24 ; 36
sbi(TCCR0A, WGM00);
6be: 84 b5 in r24, 0x24 ; 36
6c0: 81 60 ori r24, 0x01 ; 1
6c2: 84 bd out 0x24, r24 ; 36
// this combination is for the standard atmega8
sbi(TCCR0, CS01);
sbi(TCCR0, CS00);
#elif defined(TCCR0B) && defined(CS01) && defined(CS00)
// this combination is for the standard 168/328/1280/2560
sbi(TCCR0B, CS01);
6c4: 85 b5 in r24, 0x25 ; 37
6c6: 82 60 ori r24, 0x02 ; 2
6c8: 85 bd out 0x25, r24 ; 37
sbi(TCCR0B, CS00);
6ca: 85 b5 in r24, 0x25 ; 37
6cc: 81 60 ori r24, 0x01 ; 1
6ce: 85 bd out 0x25, r24 ; 37
// enable timer 0 overflow interrupt
#if defined(TIMSK) && defined(TOIE0)
sbi(TIMSK, TOIE0);
#elif defined(TIMSK0) && defined(TOIE0)
sbi(TIMSK0, TOIE0);
6d0: 80 91 6e 00 lds r24, 0x006E ; 0x80006e <__DATA_REGION_ORIGIN__+0xe>
6d4: 81 60 ori r24, 0x01 ; 1
6d6: 80 93 6e 00 sts 0x006E, r24 ; 0x80006e <__DATA_REGION_ORIGIN__+0xe>
// this is better for motors as it ensures an even waveform
// note, however, that fast pwm mode can achieve a frequency of up
// 8 MHz (with a 16 MHz clock) at 50% duty cycle
#if defined(TCCR1B) && defined(CS11) && defined(CS10)
TCCR1B = 0;
6da: 10 92 81 00 sts 0x0081, r1 ; 0x800081 <__DATA_REGION_ORIGIN__+0x21>
// set timer 1 prescale factor to 64
sbi(TCCR1B, CS11);
6de: 80 91 81 00 lds r24, 0x0081 ; 0x800081 <__DATA_REGION_ORIGIN__+0x21>
6e2: 82 60 ori r24, 0x02 ; 2
6e4: 80 93 81 00 sts 0x0081, r24 ; 0x800081 <__DATA_REGION_ORIGIN__+0x21>
#if F_CPU >= 8000000L
sbi(TCCR1B, CS10);
6e8: 80 91 81 00 lds r24, 0x0081 ; 0x800081 <__DATA_REGION_ORIGIN__+0x21>
6ec: 81 60 ori r24, 0x01 ; 1
6ee: 80 93 81 00 sts 0x0081, r24 ; 0x800081 <__DATA_REGION_ORIGIN__+0x21>
sbi(TCCR1, CS10);
#endif
#endif
// put timer 1 in 8-bit phase correct pwm mode
#if defined(TCCR1A) && defined(WGM10)
sbi(TCCR1A, WGM10);
6f2: 80 91 80 00 lds r24, 0x0080 ; 0x800080 <__DATA_REGION_ORIGIN__+0x20>
6f6: 81 60 ori r24, 0x01 ; 1
6f8: 80 93 80 00 sts 0x0080, r24 ; 0x800080 <__DATA_REGION_ORIGIN__+0x20>
// set timer 2 prescale factor to 64
#if defined(TCCR2) && defined(CS22)
sbi(TCCR2, CS22);
#elif defined(TCCR2B) && defined(CS22)
sbi(TCCR2B, CS22);
6fc: 80 91 b1 00 lds r24, 0x00B1 ; 0x8000b1 <__DATA_REGION_ORIGIN__+0x51>
700: 84 60 ori r24, 0x04 ; 4
702: 80 93 b1 00 sts 0x00B1, r24 ; 0x8000b1 <__DATA_REGION_ORIGIN__+0x51>
// configure timer 2 for phase correct pwm (8-bit)
#if defined(TCCR2) && defined(WGM20)
sbi(TCCR2, WGM20);
#elif defined(TCCR2A) && defined(WGM20)
sbi(TCCR2A, WGM20);
706: 80 91 b0 00 lds r24, 0x00B0 ; 0x8000b0 <__DATA_REGION_ORIGIN__+0x50>
70a: 81 60 ori r24, 0x01 ; 1
70c: 80 93 b0 00 sts 0x00B0, r24 ; 0x8000b0 <__DATA_REGION_ORIGIN__+0x50>
#endif
#if defined(ADCSRA)
// set a2d prescaler so we are inside the desired 50-200 KHz range.
#if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz
sbi(ADCSRA, ADPS2);
710: 80 91 7a 00 lds r24, 0x007A ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
714: 84 60 ori r24, 0x04 ; 4
716: 80 93 7a 00 sts 0x007A, r24 ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
sbi(ADCSRA, ADPS1);
71a: 80 91 7a 00 lds r24, 0x007A ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
71e: 82 60 ori r24, 0x02 ; 2
720: 80 93 7a 00 sts 0x007A, r24 ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
sbi(ADCSRA, ADPS0);
724: 80 91 7a 00 lds r24, 0x007A ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
728: 81 60 ori r24, 0x01 ; 1
72a: 80 93 7a 00 sts 0x007A, r24 ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
cbi(ADCSRA, ADPS2);
cbi(ADCSRA, ADPS1);
sbi(ADCSRA, ADPS0);
#endif
// enable a2d conversions
sbi(ADCSRA, ADEN);
72e: 80 91 7a 00 lds r24, 0x007A ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
732: 80 68 ori r24, 0x80 ; 128
734: 80 93 7a 00 sts 0x007A, r24 ; 0x80007a <__DATA_REGION_ORIGIN__+0x1a>
// here so they can be used as normal digital i/o; they will be
// reconnected in Serial.begin()
#if defined(UCSRB)
UCSRB = 0;
#elif defined(UCSR0B)
UCSR0B = 0;
738: 10 92 c1 00 sts 0x00C1, r1 ; 0x8000c1 <__DATA_REGION_ORIGIN__+0x61>
#if defined(USBCON)
USBDevice.attach();
#endif
setup();
73c: 0e 94 f1 00 call 0x1e2 ; 0x1e2 <setup>
for (;;) {
loop();
if (serialEventRun) serialEventRun();
740: c0 e0 ldi r28, 0x00 ; 0
742: d0 e0 ldi r29, 0x00 ; 0
#endif
setup();
for (;;) {
loop();
744: 0e 94 ea 00 call 0x1d4 ; 0x1d4 <loop>
if (serialEventRun) serialEventRun();
748: 20 97 sbiw r28, 0x00 ; 0
74a: e1 f3 breq .-8 ; 0x744 <main+0x8e>
74c: 0e 94 00 00 call 0 ; 0x0 <__vectors>
750: f9 cf rjmp .-14 ; 0x744 <main+0x8e>
00000752 <__subsf3>:
752: 50 58 subi r21, 0x80 ; 128
00000754 <__addsf3>:
754: bb 27 eor r27, r27
756: aa 27 eor r26, r26
758: 0e 94 c1 03 call 0x782 ; 0x782 <__addsf3x>
75c: 0c 94 2d 04 jmp 0x85a ; 0x85a <__fp_round>
760: 0e 94 1f 04 call 0x83e ; 0x83e <__fp_pscA>
764: 38 f0 brcs .+14 ; 0x774 <__addsf3+0x20>
766: 0e 94 26 04 call 0x84c ; 0x84c <__fp_pscB>
76a: 20 f0 brcs .+8 ; 0x774 <__addsf3+0x20>
76c: 39 f4 brne .+14 ; 0x77c <__addsf3+0x28>
76e: 9f 3f cpi r25, 0xFF ; 255
770: 19 f4 brne .+6 ; 0x778 <__addsf3+0x24>
772: 26 f4 brtc .+8 ; 0x77c <__addsf3+0x28>
774: 0c 94 1c 04 jmp 0x838 ; 0x838 <__fp_nan>
778: 0e f4 brtc .+2 ; 0x77c <__addsf3+0x28>
77a: e0 95 com r30
77c: e7 fb bst r30, 7
77e: 0c 94 16 04 jmp 0x82c ; 0x82c <__fp_inf>
00000782 <__addsf3x>:
782: e9 2f mov r30, r25
784: 0e 94 3e 04 call 0x87c ; 0x87c <__fp_split3>
788: 58 f3 brcs .-42 ; 0x760 <__addsf3+0xc>
78a: ba 17 cp r27, r26
78c: 62 07 cpc r22, r18
78e: 73 07 cpc r23, r19
790: 84 07 cpc r24, r20
792: 95 07 cpc r25, r21
794: 20 f0 brcs .+8 ; 0x79e <__addsf3x+0x1c>
796: 79 f4 brne .+30 ; 0x7b6 <__addsf3x+0x34>
798: a6 f5 brtc .+104 ; 0x802 <__addsf3x+0x80>
79a: 0c 94 60 04 jmp 0x8c0 ; 0x8c0 <__fp_zero>
79e: 0e f4 brtc .+2 ; 0x7a2 <__addsf3x+0x20>
7a0: e0 95 com r30
7a2: 0b 2e mov r0, r27
7a4: ba 2f mov r27, r26
7a6: a0 2d mov r26, r0
7a8: 0b 01 movw r0, r22
7aa: b9 01 movw r22, r18
7ac: 90 01 movw r18, r0
7ae: 0c 01 movw r0, r24
7b0: ca 01 movw r24, r20
7b2: a0 01 movw r20, r0
7b4: 11 24 eor r1, r1
7b6: ff 27 eor r31, r31
7b8: 59 1b sub r21, r25
7ba: 99 f0 breq .+38 ; 0x7e2 <__addsf3x+0x60>
7bc: 59 3f cpi r21, 0xF9 ; 249
7be: 50 f4 brcc .+20 ; 0x7d4 <__addsf3x+0x52>
7c0: 50 3e cpi r21, 0xE0 ; 224
7c2: 68 f1 brcs .+90 ; 0x81e <__addsf3x+0x9c>
7c4: 1a 16 cp r1, r26
7c6: f0 40 sbci r31, 0x00 ; 0
7c8: a2 2f mov r26, r18
7ca: 23 2f mov r18, r19
7cc: 34 2f mov r19, r20
7ce: 44 27 eor r20, r20
7d0: 58 5f subi r21, 0xF8 ; 248
7d2: f3 cf rjmp .-26 ; 0x7ba <__addsf3x+0x38>
7d4: 46 95 lsr r20
7d6: 37 95 ror r19
7d8: 27 95 ror r18
7da: a7 95 ror r26
7dc: f0 40 sbci r31, 0x00 ; 0
7de: 53 95 inc r21
7e0: c9 f7 brne .-14 ; 0x7d4 <__addsf3x+0x52>
7e2: 7e f4 brtc .+30 ; 0x802 <__addsf3x+0x80>
7e4: 1f 16 cp r1, r31
7e6: ba 0b sbc r27, r26
7e8: 62 0b sbc r22, r18
7ea: 73 0b sbc r23, r19
7ec: 84 0b sbc r24, r20
7ee: ba f0 brmi .+46 ; 0x81e <__addsf3x+0x9c>
7f0: 91 50 subi r25, 0x01 ; 1
7f2: a1 f0 breq .+40 ; 0x81c <__addsf3x+0x9a>
7f4: ff 0f add r31, r31
7f6: bb 1f adc r27, r27
7f8: 66 1f adc r22, r22
7fa: 77 1f adc r23, r23
7fc: 88 1f adc r24, r24
7fe: c2 f7 brpl .-16 ; 0x7f0 <__addsf3x+0x6e>
800: 0e c0 rjmp .+28 ; 0x81e <__addsf3x+0x9c>
802: ba 0f add r27, r26
804: 62 1f adc r22, r18
806: 73 1f adc r23, r19
808: 84 1f adc r24, r20
80a: 48 f4 brcc .+18 ; 0x81e <__addsf3x+0x9c>
80c: 87 95 ror r24
80e: 77 95 ror r23
810: 67 95 ror r22
812: b7 95 ror r27
814: f7 95 ror r31
816: 9e 3f cpi r25, 0xFE ; 254
818: 08 f0 brcs .+2 ; 0x81c <__addsf3x+0x9a>
81a: b0 cf rjmp .-160 ; 0x77c <__addsf3+0x28>
81c: 93 95 inc r25
81e: 88 0f add r24, r24
820: 08 f0 brcs .+2 ; 0x824 <__addsf3x+0xa2>
822: 99 27 eor r25, r25
824: ee 0f add r30, r30
826: 97 95 ror r25
828: 87 95 ror r24
82a: 08 95 ret
0000082c <__fp_inf>:
82c: 97 f9 bld r25, 7
82e: 9f 67 ori r25, 0x7F ; 127
830: 80 e8 ldi r24, 0x80 ; 128
832: 70 e0 ldi r23, 0x00 ; 0
834: 60 e0 ldi r22, 0x00 ; 0
836: 08 95 ret
00000838 <__fp_nan>:
838: 9f ef ldi r25, 0xFF ; 255
83a: 80 ec ldi r24, 0xC0 ; 192
83c: 08 95 ret
0000083e <__fp_pscA>:
83e: 00 24 eor r0, r0
840: 0a 94 dec r0
842: 16 16 cp r1, r22
844: 17 06 cpc r1, r23
846: 18 06 cpc r1, r24
848: 09 06 cpc r0, r25
84a: 08 95 ret
0000084c <__fp_pscB>:
84c: 00 24 eor r0, r0
84e: 0a 94 dec r0
850: 12 16 cp r1, r18
852: 13 06 cpc r1, r19
854: 14 06 cpc r1, r20
856: 05 06 cpc r0, r21
858: 08 95 ret
0000085a <__fp_round>:
85a: 09 2e mov r0, r25
85c: 03 94 inc r0
85e: 00 0c add r0, r0
860: 11 f4 brne .+4 ; 0x866 <__fp_round+0xc>
862: 88 23 and r24, r24
864: 52 f0 brmi .+20 ; 0x87a <__fp_round+0x20>
866: bb 0f add r27, r27
868: 40 f4 brcc .+16 ; 0x87a <__fp_round+0x20>
86a: bf 2b or r27, r31
86c: 11 f4 brne .+4 ; 0x872 <__fp_round+0x18>
86e: 60 ff sbrs r22, 0
870: 04 c0 rjmp .+8 ; 0x87a <__fp_round+0x20>
872: 6f 5f subi r22, 0xFF ; 255
874: 7f 4f sbci r23, 0xFF ; 255
876: 8f 4f sbci r24, 0xFF ; 255
878: 9f 4f sbci r25, 0xFF ; 255
87a: 08 95 ret
0000087c <__fp_split3>:
87c: 57 fd sbrc r21, 7
87e: 90 58 subi r25, 0x80 ; 128
880: 44 0f add r20, r20
882: 55 1f adc r21, r21
884: 59 f0 breq .+22 ; 0x89c <__fp_splitA+0x10>
886: 5f 3f cpi r21, 0xFF ; 255
888: 71 f0 breq .+28 ; 0x8a6 <__fp_splitA+0x1a>
88a: 47 95 ror r20
0000088c <__fp_splitA>:
88c: 88 0f add r24, r24
88e: 97 fb bst r25, 7
890: 99 1f adc r25, r25
892: 61 f0 breq .+24 ; 0x8ac <__fp_splitA+0x20>
894: 9f 3f cpi r25, 0xFF ; 255
896: 79 f0 breq .+30 ; 0x8b6 <__fp_splitA+0x2a>
898: 87 95 ror r24
89a: 08 95 ret
89c: 12 16 cp r1, r18
89e: 13 06 cpc r1, r19
8a0: 14 06 cpc r1, r20
8a2: 55 1f adc r21, r21
8a4: f2 cf rjmp .-28 ; 0x88a <__fp_split3+0xe>
8a6: 46 95 lsr r20
8a8: f1 df rcall .-30 ; 0x88c <__fp_splitA>
8aa: 08 c0 rjmp .+16 ; 0x8bc <__fp_splitA+0x30>
8ac: 16 16 cp r1, r22
8ae: 17 06 cpc r1, r23
8b0: 18 06 cpc r1, r24
8b2: 99 1f adc r25, r25
8b4: f1 cf rjmp .-30 ; 0x898 <__fp_splitA+0xc>
8b6: 86 95 lsr r24
8b8: 71 05 cpc r23, r1
8ba: 61 05 cpc r22, r1
8bc: 08 94 sec
8be: 08 95 ret
000008c0 <__fp_zero>:
8c0: e8 94 clt
000008c2 <__fp_szero>:
8c2: bb 27 eor r27, r27
8c4: 66 27 eor r22, r22
8c6: 77 27 eor r23, r23
8c8: cb 01 movw r24, r22
8ca: 97 f9 bld r25, 7
8cc: 08 95 ret
000008ce <_exit>:
8ce: f8 94 cli
000008d0 <__stop_program>:
8d0: ff cf rjmp .-2 ; 0x8d0 <__stop_program>
What am I missing?