USART Divider of 2 to get to 571428 baud ?

Hi all,

I’ve done quite a bit of interfacing of products at data-rates from 9600 baud to 250,000 baud, but a current project I’m working on demands a rate of ~571,428 baud (Which is 1/28 of 16,000,000). The USART’s on the Atmega328 & Atmega2560 processors are at the pointy end of the baud rate register UBRRn, where (using Asynchronous Double Speed Mode U2Xn = 1) a UBBRn of 3 yields 500000 and a UBBRn of 2 yields 666666. 2.5 would nail the baud rate at 571,428… If 2.5 were possible.

If I could operate in Synchronous mode, I could use a UBBRn of 13 and get my 571,428… But I’ve tried setting UBBRn to 13 and UMSELn to 01… and it just silences the output. it compiles fine and the arduino is running (it’s reporting back to me on the serial monitor on USART0) buy my logic analyser receives nothing.

I tried setting the DDR_XCKn bits to output, though this isn’t documented all that clearly in the Atmel documentation. My method is: DDRJ |=(1<<PJ1) (for the XCK3 pin on the Atmega2560 - I’m using UART3).

So my questions are:

  • Is synchronous mode a realistic option? I’m just going out of the USART into a Maxim MAX3467 RS-422 transceiver, so I’d be using synchronous mode purely to get the math right for the baud rate.
  • Am I configuring DDR_XCKn correctly?
  • Is there another way to get the divider to 2? Atmel describes it in its documentation as a ‘High Resolution Baud Rate Generator’ - it certainly isn’t at this end!

I’d be very appreciative of any wisdom you can bring! :slight_smile:

You cannot use synchronous mode for asynchronous operation. If you use synchronous mode the baud rate is just a selection of the speed. The clock signal is mandatory then the signal will be scanned at the chosen edge regardless if that clock signal drifts in some way. As the MAX3467 doesn't have a clock signal input (or output) I would not expect that to work.
The reason why asynchronous operation doesn't allow the same high bit rates as the synchronous operation is the baud rate adaption. In synchronous mode this adaption isn't necessary as the clock signal defines exactly when a bit value is available.