So this is probably a bit of a dumb question but I'm having trouble understanding the guides and totorials on the vias - for some reason. I am laying out a board in KiCad that I would like PCBway to make for me. This is my second design that i'll be sending out, but my first double layer board.
As I understand it, I will draw the trace on the bottom of the board from my Arduino pin (for example), pop in a via to send the trace to the top of the board, run it close to where i need it, pop in another via to get the trace to the bottom, then connect the trace to its destination solder pad on the bottom. When i receive the board all I'll have to do is solder the Arduino and destination pins - the vias will be set up by the board maker and covered by the solder mask.
Assuming that's all correct, is there anything else I should keep in mind with vias? Should i try to avoid them for i2c? My board is using digital high/low for sensor on/off (very much not high speed), i2c, and of course power/gnd.
newneo_phyte:
So, madness of placing each trace by hand aside, how do the vias work?...
I don't think it is madness but rather common practice. Autorouting seems to be mostly used for
a) partial routing, like BGA fanout (though I think that can also be worth doing manualy) and
b) on stuff that doesn't really matter (Like "We don't care if we need a 10 layer board for this, we just need it running really fast"
What you describe is just "vias" in general.
"tenting" vias refers to the practice of modifying the soldermask so that the copper rings on either side are covered by the soldermask material; otherwise they would look like small pads, bare for soldering.
Most autorouters tend to try to minimize vias; you probably should too. But I'm not entirely sure whether it's due to signal integrity issues, reliability issues, or cost issues (that no long seem applicable - at one time, the cost to manufacture a PCB would go up for each hole.)
Only think to check is you set them up according to spec from the fab house. Aka, drill size and clearance larger then fab house minimum. No difference then for traces.
Aside from that, just use them but don't go mad. And for through hole it does not matter if you connect the trace on the top or bottom. You can start and stop on both top or bottom layer. But KiCad will tell you (by not making it possible to do it wrong :p)
I just had that discussion a few days ago. My nonprofessional opinion is:
If we are not dealing with difficult signals (i.e. especially high frequency, differential signals and such), rather keep the board tidy than cut the via count. When routing e.g. (long) horizontal traces on the back and vertical traces on the front, then some vias a necessary. I would set them, even if I could avoid switching layers in the current design. I might want to change something, route another trace, and then run into issues.
In my experience, vias are best avoided by intelligent placement of the components, not by routing differently.
But since that is my nonprofessional opinion, I would like to hear others.
Advanced question: Is the trace between a decoupling cap and the IC a "difficult signal" trace? Would I want to avoid vias, or would I use them to keep the cap as close to the IC as possible? I am thinking e.g. of ICs like the ISO1540, where GND is on one side, Vcc on the other they are separated by the signal pins.
ElCaron:
Advanced question: Is the trace between a decoupling cap and the IC a "difficult signal" trace? Would I want to avoid vias, or would I use them to keep the cap as close to the IC as possible? I am thinking e.g. of ICs like the ISO1540, where GND is on one side, Vcc on the other they are separated by the signal pins.
Basically routing a decoupling cap seeks to minimise the "loop area" enclosed by the tracks to the cap. On some multi-layer boards, the loop area being considered is on the vertical plane.
Wave soldered will make the solder go up under the component
Ah. Another reason for actual "tenting", I guess.
Most of the "lots of vias under a component" show up in fine-pitch SMT designs (ie Due has 50ish vias under the ARM chip) that aren't wave-soldered anyway.