Hi,
I'm trying to get an as clean as possible DAC output from the samd21 CPU (Arduino Zero microcontroller). The datasheet gives two major information about VDDANA and GNDANA (the power pins which are connected to the DAC, ADC, 32kHz crystal etc) :
In section 8.2.1 (p38) : "The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as V
DD in the datasheet."
Section 39.2.1 (p1017) : The schematic shows a ferrite bead from 3.3V supply to VDDANA, and a 10uF and 100nF cap from VDDANA to GNDANA (after the ferrite). There is also a "global" 10uF cap on the 3.3V power supply (before the ferrite).
My question is : if I want to prevent any audible noise, is that filtering sufficient?
I was thinking about using a RC low pass filter after the ferrite bead, instead of the 2 caps : (10-20Ω and 47µF, Fc around 150-350Hz). The problem with the RC filter is the series resistor : it breaks the first rules of the datasheet where alla VDD votlage should be the same, because of the voltage drop around the resistor (60mV max with an estimated max VDDANA current of 3mA).
Do you think that it is a bad idea to put 3.24V on the VDDANA pin while there is 3.3V on the other VDD pins (VDDIO and VDDIN)?
Thanks in advance guys 