VFD SAMSUNG 96L08AA3

From older equipment I have couple of VFD Samsung 96L08AA3 and I would like to use them, does have somebody idea how to use them?

THX

96L08AA3.pdf (403 KB)

If you don't know what you're talking about, you shouldn't give advice to anyone. Don't tell people to wire their devices with pins that say CLK and SDA to connect it to either Rx or Tx.

CLK and SDA hint to I2C, but i don't see anything about addressing, which is an important part of I2C.

It's more like SPI, but i'm not sure about that either. Usually SPI has some additional addressing pins telling devices data is meant for them. But those seem to be missing in this module.

Could use SPI, but it looks like you'll need to try the RST line as a Slave Select (inverted) or just have it as the only SPI device connected. Max clock rate is 2MHz.

This is a very good candidate for just bit-banging the data. Arduino's shiftOut() will do this.

Using an Uno, here's the timing for CLK and SDA (sending 0x55)...

|500x136

Looks to be very compatible with datasheet timing diagram...

|500x139

MAS3: If you don't know what you're talking about, you shouldn't give advice to anyone. Don't tell people to wire their devices with pins that say CLK and SDA to connect it to either Rx or Tx.

CLK and SDA hint to I2C, but i don't see anything about addressing, which is an important part of I2C.

It's more like SPI, but i'm not sure about that either. Usually SPI has some additional addressing pins telling devices data is meant for them. But those seem to be missing in this module.

I read the datasheet and told what I understood. I am also working on vfd's.

According to the datsheet 4.7.1 page 5, the /RST signal has two functions. - clear/flush serial data buffer - reset everything

If it is asserted for > 50us up but less than 2ms the serial buffer is cleared. If it is asserted for >2ms everything is reset.

The short pulse reset to clear the serial buffer is nice as it can be used to ensure that stray glitches on the clock signal during powerup don't clock in stray bits which can cause the host and the part to get out of sync.

This is a feature sorely lacking in the AVR ISP programming interface.

--- bill

creativerightside: I read the datasheet and told what I understood. I am also working on vfd's.

You are not understanding the datasheet for this device. While the data is being sent serially, it is not using asynchronous serial. Go have another read of section 4.7.2 on page 5. It explains how to transfer data to the device. It is using SPI.

Many devices that claim to be SPI are not actually SPI but simply using a shift register. That is why they need a slave/chip select signal. Many devices use a /ss or /cs signal to know when to latch the data. A true SPI interface can clock in data bits essentially forever and requires no latching signal to indicate when to latch the data. The /ss signal is merely used to allow multiple SPI devices to share the same data and clock signals. And that is why it is so important to keep the host and device in sync since if there is no /cs signal, there is no way to ever get back in sync. At least with this device you can use the /RST signal to ensure the host and the device are sync.

--- bill

In case you need to reserve the main SPI for another device, you can use the USART in MSPIM mode.

On Uno:

Pin 1 TX (SDA)
Pin 4 T0 (CLK)

MSPIM set to SPI Mode 1, 2MHz clock rate.

Here’s the setup test code…

byte data = 0x55;

void setup() {
  USART_MSPIM_Init();
}

void loop() {
  if ((UCSR0A & 32) != 0) { // transmit when data register empty
    UDR0 = data;
  }
  delayMicroseconds(10);
}

void USART_MSPIM_Init()
{
  UBRR0H = 0;
  UBRR0L = 0;
  DDRD |= _BV (4);                                             // XCK as output enables master mode
  UCSR0C = (1 << UMSEL01) | (1 << UMSEL00) | (1 << UCPHA0) | (0 << UCPOL0); // Master SPI, mode 1
  UCSR0B = (1 << RXEN0) | (1 << TXEN0);                        // Enable receiver and transmitter
  UBRR0L = 3;                                                  // 2MHz XCK on pin 4
}

Here’s the timing…