You need your oscillator feeding a shift register parallel in serial out, the shift register is fed with a parallel output of a dual ported RAM chip. Then the address lines on your RAM are fed with a counter derived from the a divide by 8 of the origional oscillator.
At some point you have divided this down enough with the RAM address counter that it is slow enough to trigger an interrupt and have the ISR fill up the RAM through its other port.
Or forget the dual ported RAM and have some logic chips generate a test pattern.