Theory (and the datasheet) says that the watchdog control register is reset to the default value of zero (except for the Enable bit) on a reset, which would mean that a freshly reset chip is always operating with the minimum timeout. 
I think that's silly; if you're going to remember that the WDT is running, you should remember other things about it as well; but it does make sense from a HW perspective, and seem to match observed behavior.