What did I miss about ADC and Clock

Official Hardware Portenta Family Portenta H7
1

For my project I tried to get more accurate results out of the Portenta's ADC. Thus I tried increasing the number of clock cycles to get a sample to 810.5 cycles and I must say I am quite satisfied of the results. However that increase in clock cycles drastically reduced my sampling rate (from 200 kHz to 20kHz).
The solution I found to this issue is to increase the ADC Clock frequency, what lead me to setup the pll3_r_ck (code below).

void Conf_New_CLCK(void){
  /***************Deactivate PLL3***********************/
  CLEAR_BIT(RCC->CR,RCC_CR_PLL3ON_Msk);
  while (RCC_CR_PLL3RDY & RCC_CR_PLL3RDY_Msk == 1) {}   
  /***************Select CLCK source Ref***************/
  //CLEAR_BIT(RCC->PLLCKSELR,) //PLLSRC HSI 00
  /******************Source ref Frequency**************/
  SET_BIT(RCC->CR,RCC_CR_HSIDIV_8);//Must not go over 12 MHZ in input as ref for PLL(so 8MHz)
  /*******************DIVM3****************************/
  //SET_BIT(RCC->PLLCKSELR,RCC_PLLCKSELR_DIVM3_0 | RCC_PLLCKSELR_DIVM3_1 | RCC_PLLCKSELR_DIVM3_2 | RCC_PLLCKSELR_DIVM3_3 | RCC_PLLCKSELR_DIVM3_4 | RCC_PLLCKSELR_DIVM3_5);  //To re setup ref  
  /*******************VCOSEL***************************/
  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL_Msk);//VCOH chosen for ref above 2MHz
  /*******************PLL3RGE**************************/
  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE_0 | RCC_PLLCFGR_PLL3RGE_1);//Frequency range of the ref inbetween 8 and 16 MHz
  /*******************Integer mode*********************/
  CLEAR_BIT(RCC->PLLCFGR,RCC_PLLCFGR_PLL3FRACEN_Msk);
  /********************DIV3 P/Q/R EN*******************/
  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN_Msk | RCC_PLLCFGR_DIVQ3EN_Msk); //Only PLL3_R_CK output
  /********************DIVR3***************************/
  RCC->PLL3DIVR&=~(1<<24); //No division fact on PLL3 
  /********************DIVN3***************************/
  RCC->PLL3DIVR|=(0x1FF<<0);//Default value 129 
  /********************PLL3 ENABLE*********************/
  SET_BIT(RCC->CR,RCC_CR_PLL3ON_Msk);
  while (RCC_CR_PLL3RDY & RCC_CR_PLL3RDY_Msk != 1) {}   
  /*******************CLCK for ADC*********************/
  SET_BIT(RCC->D3CCIPR,RCC_D3CCIPR_ADCSEL_0);
}

For the ADC to go for the clock I configured in my ADC configuration I put ADC CKMODE to 00. And by using a GPIO to output a pulse whenever DMA requests are completed I can confirm that despite having 810.5 clock cycles I get the desired frequency (ADC is triggered by a timer). However when I read the ADC register or the DMA buffers all I get are zeroes?
What may I have done wrong, this is definitely linked to the pll3 (not the pll itself but how I did set it up).

EDIT : Testing with different values of DIVN3 I still have ADC results for DIVN3=129 (which is not enough in term of sampling frequency for 810.5 clock cycles) but not anymore for DIVN3=257. How does that make sense I don't get it?
Little schematics to visualize better what I am doing :

image
(x=1,2,3)
image

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