[quote author=Coding Badly link=topic=92100.msg693461#msg693461 date=1329419067]
Does the C RTL zero =all= of SRAM
No. The bss section is zeroed. The data section is copied from Flash. The rest is left untouched.
Udo Klein has something that may help...
Bear in mind that the memory is [u]not initialized, ever[/u]. It will have "random" data in it after power-up.
On a side-note, I suspect Udo could not get it working reliably because of this problem...
Right now I'm trying to restore output pin states faster than it will take for the Modbus "read coils" and "force coil" commands to do that. If I can do that in fewer than 10 AC cycles (167ms), I'd be happy. If I can do that in under 3 AC cycles (50ms), I'll jump for joy. Both of those goals require that I can have the state tucked away in some special place in SRAM and not have it zero'd across resets.
Just remember that Atmel makes no guarantees about the state of SRAM after a reset. At a minimum, you should put magic values on each end of the data and include a CRC.[/quote]
I believe there is a "reset reason" status register that can tell me if I reset due to reset pin, power on or watchdog reset. If the reason is "watchdog reset", I can assume (hah!) that my value is correctly stored in some secret, magical, non-BSS location.
I don't want to write it to EEPROM due to it having a limited life expectancy
You expect more than 100,000 writes during the lifetime of the device?
D'oh! I mixed up FLASH cycles and EEPROM cycles. I'll have to look at using EEPROM to store state before the watchdog reset is scheduled. There are times when I'm glad to feel embarrassed ...