I have seen in several schematics, but most recently that of the Due, where there are several equivalent capacitors in parallel. The Due has 6 x 100n caps (eight if you count the ones in series with inductors) in parallel across the 3.3v supply. I initially thought the this was to get a high capacitance rather than putting in a big single cap. However on closer inspection there are a couple of 10uF in parallel with the 100n's, so they are not averse to putting in higher values. Therefore what is the point of so many caps when you can get the same effect (filtering out HF ripple with the small values and buffering voltage for transient high demand with high values) by using say 1 x 100n and a 47uF? i.e. replacing 10 components with 2? What do they know that I don't?
Hi.
Have another look at the schematics, and at the PCB.
To have the schematics look better and a bit easier to read, all capacitors on the power rails are grouped.
The schematics do however have no relation to the actual position on the PCB of the component.
The caps (perhaps pair of caps), are all spreaded out on the PCB, so they are close to the component they are meant to serve.
This way longer traces can't spoil the effect of the capacitors.
So the caps are in parallel as drawn, but they actually aren't all next to each other on the board.
Thanks MAS3. Duh, I should have realised that.
In simple terms all pcb tracks have inductance and will cause the impedance of the HF decoupling capacitors to rise if they are far from the ICs where they are needed. In more detail they are transmission lines which have delay and coupling to other tracks. It is best to keep all high frequency current paths as short as practical to avoid unwanted coupling.
Russell.
From here.
"Since capacitors differ in their high-frequency characteristics (and capacitors with good high-frequency properties are often types with small capacity, while large capacitors usually have worse high-frequency response), decoupling often involves the use of a combination of capacitors. For example in logic circuits, a common arrangement is ~100 nF ceramic per logic IC (multiple ones for complex ICs), combined with electrolytic or tantalum capacitor(s) up to a few hundred μF per board / board section."
Edit: Whoops. Answered the wrong question. Haven't had my morning coffee yet.