What to expect after clock division (CLKPR, ATmega328P)

Projects Programming
1

Hello,

I have a custom board which is equipped with ATmega328 and an 8MHz external oscillator.
As the functions which are completed by the uC are not "calculation heavy", I was wondering whether I should divide the clock and use the uC at 2MHz for example. Between external interrupts, the uC is put to sleep, when the uC is awake (and can't go to sleep) it does some analog readings, UART and I2C (100 and 400kHz) communications (which execution times are not dependent on the uC clock in the MHz range as far as I know). Although I know that the uC clock and the chosen UART clock has to be "compatible".

I checked 2MHz and 9600kb here, and it seems OK.

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I'm aware of the fact that I would have to change the F_CPU define to match the divided clock and then millis and micros functions would still be accurate.

My question is what else should be considered when slowing down the clock like this?

Thanks in advance.

2

I can't answer the question with certainty.

It might however be easier to forget about the external oscillator and just use the internal oscillator. If you install MiniCore you will have the option for an internal 2MHz clock and everything will be adjusted.

3

I used external clock source, because I don't want to bother with internal oscillator calibration (asynchronous UART needs accurate clock, and the internal oscillator is only guaranteed within 10%).

4

I don't think there is anything that does not depend on the clock.

5

"Common wisdom" is that overall power consumption is lower at higher clock rates, because the chip spends less time "awake."

6

Yes, but time spent awake is not "calculation heavy". During the peak consumption period, communication is only done with the UART device (GSM modem).

On second thought, with the modem's 300mA consumption, there's not much point in messing around with this 2mA that could be saved with a 2MHz clock.