If both lines are high when null then the following would be true, wouldn't it?
Assuming you're talking about the A and B line, they should never both be high as I'm sure that will be an undefined state on the line.
TBH I can't follow all the HI/LO/LO/HI stuff (well I'm sure I could but life's to short :)), all the talk about the actual RS-485 signal lines is really confusing the issue, until you have electrical problems the two signal levels are immaterial, it's the Txd and Rxd data signals on your UART that count.
Failsafe biasing ensures that when the line is not being driven the logic level presented on the RO pin and therefore to the Rxd pin is HIGH. The biasing is usually a ~560R resistor from A to VCC and another from B to GND. This is such a standard that in fact it's often built into the transceiver chips and I suspect applying resistors in any other combination (except adding the normal 120R terminator if required) may cause problems.
Have a look at Nick's tutorial here
So FS biasing ensures that an idle line is high but has no affect when the line is being driven high, that requires different wiring of the transceiver.
Now the bog-standard-used-by-every-man-and-his-dog method of doing this sort of thing has the line being driven low (assertive level) and let go to hi-z for a high (recessive level). This can be done many ways, open-collector, open-drain, tri-state buffers etc but if you want to use RS-485 you have to get a bit clever and wire the transmitter as I mentioned above.
If done properly such a system is non-destructive so you don't lose any data if there's a clash.
Which brings us to the "done properly" part.
- Split the bit into phases, 'error check' and 'valid data'.
This would allow a device attempting to send a recessive bit to identify the error and release the lines before other devices on the bus read the data.
That's essentially correct, receivers typically read the bit at the 50% point but as long as you use a non-destructive scheme I don't think that matters as long as the overridden transmitter releases the line before the next bit starts.
So the code has to be very tight relative to the bit rate. In other words if it takes you 150uS to detect the clash and the bit time is 100uS then you will corrupt the data. Depending on your bit rate this normally means no long-winded function calls, probably putting all the transmit code in a single function.
What bit rate do you have in mind?
I would like to try and do this, first experiments anyway, directly with the 5v digital pins.
So you transmit an active low but for highs you make the Tx pin an input to tri-state it.
Rob