Why this latching circuit automatically turn on

Hi everyone!
I need some help regarding to this picture below I had run some simulation and after I'm running the simulation the circuit is automatically power on before pushing the momentary push button. I hope that you can give some suggestion to fix the circuit without adding new component. thank you very much
image

I will take a SWAG and say it turns on if there is no load. What effect does the 1uF cap have on the circuit?

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I'm not sure about that and thank for the answer can i know how to make a 0V when the the switch are open? thank you

This is certainly the most plausible explanation that I can see since the network including the gate of the NMOS is effectively floating at power on if there is no load. Did you simulate it which the load attached (say a 1k resistor). Show the actual circuit from your simulator.

Yes, agreed, there's nothing to hold the lower MOSFET gate low if there's no load.

image
this is my circuit when i run simulation but im refer to previous circuit. As you can see when the circuit is open the voltage same as supply and now i dont know how to get 0V when the switch is open. Any suggestion? thank you

Of course. It has been hinted at in 3 posts in this thread. Try putting a 1K resistor across J1 resistor to simulate a load. That should prevent the unwanted output voltage appearing on power up.

C1 is charged through R1 and R2. Once it reaches the threshold of Q2A's gate, Q2A starts to conduct, taking Q2B with it and the circuit turns on.

It could also be my eyesight, or due to the poor image quality, but the ground on Q2A in the simulation doesn't appear to be a strong connection.

thank you for the suggestion i tried and its works, thank you very much but there is another problem which is the voltage are not same which is 17V. I expected when im running the simulation, when the switch is open, it will be 0V and after push the momentary button which is closed the voltage will be 17V

So what voltage(s) are you measuring in which places?

The component values for that circuit appear very critical. I used LTspice to simulate it covering the power on, press 1 of the latch to power the load and press 2 of the latch to switch off the load. I haven't got a model for that mosfet IRF7319 so I attempted to find something similar and modified some values (also added a small capacitor). The output voltage reaches the input voltage (17 volts).

woww that is amazing and thank you for helping me. I had tried it on proteus but the output are not same. can you explain how the circuit flow? thank you very much.

Dangerous circuit.
17volt is very close to the absolute max source/gate voltage of most mosfets.
Leo..

I won't explain it in detail because that is probably the exercise you have been given (and anyway I would probably not make a very good job of it).
What I can do is give you the LTspice file as an attachment and LTspice is free to download but is not in the same league as Proteus (which you clearly have access to). However you do it, you have to watch the 3 phases, that is (1) start up, (2) the first press of the switch to latch the circuit on, and (3) the second press of the switch to latch it off. You can zoom in to a granularity of a few microseconds at these critical points. Most of the complexity was in parametrising the voltage controlled switch and finding mosfets which had a reasonable similarity to the IRF7319 (dual N/P MOS). Also, and probably most difficult, fine tuning the component values to allow the circuit to power up in the off state with only a 1k load. See also here: mosfet - PMOS Turn-On due to gate capacitance? - Electrical Engineering Stack Exchange
One tip. Surely Proteus allows you to rotate and mirror the mosfets to give the circuit layout a cleaner look than you achieved in post #6.
The comment from @Wawa is valid and zener diodes are sometimes used to keep Vgs in range (however, these have a capacitance which may also disturb the delicate balance of that circuit). Good luck with it.

LTspice file
latch with voltage controlled switch V0_03.zip (858 Bytes)

Full 10 second time line with only output voltage shown

Several sample voltage measurements across the range

The first 50uS

Latch on

Latch Off

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