Why use an and gate this way?

Can anyone explain the purpose of using an AND gate with both inputs tied together? See below for an example.

AndGate.bmp (347 KB)

It is just being used as a non inverting buffer.
If it were a NAND gate it would be an inverting buffer.

It is also essential to ensure that "spare" inputs are not left "floating". If the spare is not tied to logic '1" then it is quite notmal to parallel inputs to fully define the input state

(no electrical guru) it also "squarifies" a pulse again ...

Might be giving a really low drive capable signal some more drive cability too:
±4-mA Output Drive at 5 V

TTL logic families have a fanout rule, such that an output can only reliably drive up to 10 inputs, so if a given signal is already used up most of it's fan out then you need to buffer it through a gate to gain another 10 fanouts. So that application is most likely being used as a buffer.

I have sometimes seen such other wise 'useless' logic gate used to slow down a signal by the propagation delay of the gate for timing purposes.


Back in the stone age I remember the claims made about the number of transistors used in a given portable radio. Some of the so-called 10 transistor radios, which were supposedly better than the 6 transistor variety, just had four of them configured and used as diodes.


True I remember that. It also reminds me of the way the said how many jewels there was in a watch.